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    • 7. 发明申请
    • ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT
    • 估计电子电路的功耗
    • US20120216160A1
    • 2012-08-23
    • US13365961
    • 2012-02-03
    • Thomas BuechnerMarkus BuehlerPhilipp PanitzLei WangMarkus Olbrich
    • Thomas BuechnerMarkus BuehlerPhilipp PanitzLei WangMarkus Olbrich
    • G06F17/50
    • G06F17/5022G06F2217/78G06F2217/84
    • A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.
    • 一种方法包括估计电子​​电路的功耗。 估计包括基于用于全电路计算的电子电路的等级化结果将至少一个门的第一门分配到优先级队列中,并且将至少一个门的第二门分配到优先队列中,该优先队列中的扇出 栅极直接连接到调整大小的门的扇入栅极用于增量电路计算。 对于来自优先级队列的每个门,该估计包括执行以下操作。 通过静态时序分析和将毛刺窗口计算为差异来确定门的输出网络处的最新和最早的信号到达时间,并且基于毛刺窗口为输出网络计算转移度量。 这些操作包括确定信号转换的上限,以及基于上限来估计功耗。
    • 9. 发明授权
    • Glitch power reduction
    • 毛刺功率降低
    • US08407654B2
    • 2013-03-26
    • US13365972
    • 2012-02-03
    • Thomas BuechnerMarkus BuehlerMarkus OlbrichPhilipp PanitzLei Wang
    • Thomas BuechnerMarkus BuehlerMarkus OlbrichPhilipp PanitzLei Wang
    • G06F17/50
    • G06F17/505G06F2217/78
    • A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.
    • 一种方法包括降低电子电路的功耗,其中电子电路包括至少一个具有至少一个具有单个输出网的门的逻辑锥,其中至少一个门的表示是来自标准单元库的元件的实例。 降低功耗包括通过计算每个门的转换度量和功率度量来确定动态功耗的上限。 降低功耗包括选择具有大于预定阈值的功耗上限的门。 对于每个所选择的门,执行操作包括:通过针对所述多个配置中的每一个计算相应的功耗上限来测试来自所选择的门的标准单元库的多个配置; 选择门极配置,最小上限为功耗; 以及根据选择的门配置修改门级设计表示。