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1. 发明授权

US06874105B2 Operation graph based event monitoring system 失效
标题翻译：基于操作图的事件监控系统
公开(公告)号：US06874105B2
公开(公告)日：2005-03-29
申请号：US09997048
申请日：2001-11-29
申请人： Thomas Buechner , Rolf Fritz , Markus Michael Helms , Kirk David Lamb , Thomas Schlipf , Manfred H. Walz
发明人： Thomas Buechner , Rolf Fritz , Markus Michael Helms , Kirk David Lamb , Thomas Schlipf , Manfred H. Walz
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/3471 , G06F11/3447 , G06F2201/835 , G06F2201/86
摘要： A non-obtrusive activity monitor is proposed for advantageously monitoring and tracing disjunct, concurrent computer system operations in heavily queued computer systems. For each traced and pending computer system operation, the monitor uses a hardware implementation of an event triggered operation graph to trace the path of the computer system operation through the computer system. For each followed path, a unique signature is generated that significantly reduces the amount of trace data to be stored. In a preferred embodiment, the trace information is stored together with a time stamp for debugging and measuring queuing effects and timing behavior in a computer system.
摘要翻译：提出了一种非突出的活动监视器，用于有意义地监视和跟踪大量排队的计算机系统中的分离的并发计算机系统操作。对于每个跟踪和待处理的计算机系统操作，监视器使用事件触发操作图的硬件实现来跟踪计算机系统通过计算机系统操作的路径。对于每个跟随的路径，生成唯一的签名，显着减少要存储的跟踪数据的数量。在优选实施例中，跟踪信息与时间戳一起存储，用于在计算机系统中调试和测量排队效果和计时行为。

2. 发明授权

US07830737B2 SMI memory read data capture margin characterization circuits and methods 有权
标题翻译： SMI存储器读取数据采集裕度表征电路和方法
公开(公告)号：US07830737B2
公开(公告)日：2010-11-09
申请号：US12147685
申请日：2008-06-27
申请人： Kirk David Lamb
发明人： Kirk David Lamb
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/006 , G11C29/50012
摘要： The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system.
摘要翻译：本发明涉及诸如连接到SDRAM的接口ASIC等存储器件的边缘特性。电路和方法在晶片测试期间在芯片上执行裕度表征; 然而，表征也可以在模块测试或系统中执行。

3. 发明申请

US20090249174A1 Fault Tolerant Self-Correcting Non-Glitching Low Power Circuit for Static and Dynamic Data Storage 审中-公开
标题翻译：用于静态和动态数据存储的容错自校正无毛刺低功率电路
公开(公告)号：US20090249174A1
公开(公告)日：2009-10-01
申请号：US12060593
申请日：2008-04-01
申请人： Kirk David Lamb
发明人： Kirk David Lamb
IPC分类号： G06F7/04 , G06F11/07
CPC分类号： H03K19/007 , H03K19/0008
摘要： In a computer system in which personalization data for an ASIC is stored in latches, this data is susceptible to soft errors. Many computer systems require high levels of error detection, error correction, fault isolation, fault tolerance, and self-healing. In order to complete an ASIC design and release it to a foundry, it must first be verified that the design meets the frequency requirements of its specification. A fault tolerant, self-correcting, non-glitching, low power circuit is described which meets all the requirements for reliability, while also eliminating any requirement to add area or power to the ASIC in order to meet the frequency specification for personalization latches. By using the circuits as a repeatable structure, the verification of the self-healing property is simplified relative to a collection of Error Correction Code usages of various bit widths.
摘要翻译：在其中存储用于ASIC的个性化数据的计算机系统中，该数据容易受到软错误的影响。许多计算机系统需要高水平的错误检测，纠错，故障隔离，容错和自愈。为了完成ASIC设计并将其发布到代工厂，必须首先验证设计符合其规范的频率要求。描述了容错，自校正，无毛刺，低功率电路，其满足可靠性的所有要求，同时还消除了为了满足个性化锁存器的频率规范而向ASIC添加面积或功率的任何要求。通过将电路用作可重复结构，相对于各种位宽度的误差校正码使用的集合，简化了自修复属性的验证。

4. 发明授权

US08661382B2 Modeling for soft error specification 有权
标题翻译：软错误规范建模
公开(公告)号：US08661382B2
公开(公告)日：2014-02-25
申请号：US12637016
申请日：2009-12-14
申请人： Kirk David Lamb
发明人： Kirk David Lamb
IPC分类号： G06F17/50 , G06F11/22 , G06G7/62
CPC分类号： G06F17/5009
摘要： Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating.
摘要翻译：电路软误差建模。从设计条目接收到软错误（SEU）规范和设计信息。 SEU规范包括节点的预期SEU行为。基于SEU规范和设计信息创建逻辑仿真模型。基于逻辑仿真模型执行逻辑验证以产生第一结果。逻辑验证包括选择用于注入的第一节点，将SEU注入到第一节点中以产生第一结果，并且响应于不符合SEU规范的第一结果，将第一结果提供给设计条目。创建基于SEU规范和设计信息的网表。网表包括从SEU规范派生的基于规范的逻辑降额。执行基于网表的物理设计验证，逻辑降额和时钟信息。它包括基于基于规范的逻辑降额来计算节点故障时间。

5. 发明申请

US20110145771A1 Modeling for Soft Error Specification 有权
标题翻译：软错误规范建模
公开(公告)号：US20110145771A1
公开(公告)日：2011-06-16
申请号：US12637016
申请日：2009-12-14
申请人： Kirk David Lamb
发明人： Kirk David Lamb
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating.
摘要翻译：电路软误差建模。从设计条目接收到软错误（SEU）规范和设计信息。 SEU规范包括节点的预期SEU行为。基于SEU规范和设计信息创建逻辑仿真模型。基于逻辑仿真模型执行逻辑验证以产生第一结果。逻辑验证包括选择用于注入的第一节点，将SEU注入到第一节点中以产生第一结果，并且响应于不符合SEU规范的第一结果，将第一结果提供给设计条目。创建基于SEU规范和设计信息的网表。网表包括从SEU规范派生的基于规范的逻辑降额。执行基于网表的物理设计验证，逻辑降额和时钟信息。它包括基于基于规范的逻辑降额来计算节点故障时间。

6. 发明申请

US20090322376A1 SMI MEMORY READ DATA CAPTURE MARGIN CHARACTERIZATION CIRCUITS AND METHODS 有权
标题翻译： SMI存储器读取数据捕获标志符号电路和方法
公开(公告)号：US20090322376A1
公开(公告)日：2009-12-31
申请号：US12147685
申请日：2008-06-27
申请人： Kirk David Lamb
发明人： Kirk David Lamb
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G11C29/50 , G11C29/006 , G11C29/50012
摘要： The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system.
摘要翻译：本发明涉及诸如连接到SDRAM的接口ASIC等存储器件的边缘特性。电路和方法在晶片测试期间在芯片上执行裕度表征; 然而，表征也可以在模块测试或系统中执行。

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