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1. 发明授权

US07041568B2 Method for the production of a self-adjusted structure on a semiconductor wafer 失效
标题翻译：在半导体晶片上制造自调整结构的方法
公开(公告)号：US07041568B2
公开(公告)日：2006-05-09
申请号：US10485307
申请日：2002-07-18
申请人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L21/0274
摘要： A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle Θ of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.
摘要翻译：半导体晶片的层表面上的结构具有至少一个反射用于电磁辐射的第一区域区域（8,9）和至少一个第二基本上不反射区域区域（10,11,12）。在所述层表面上产生透光绝缘层（13）和感光层。将电磁辐射以角度引导到感光层上。入射角和层表面的结构以横向偏移成像到感光层中。

2. 发明授权

US06806037B2 Method for producing and/or renewing an etching mask 失效
标题翻译：用于制造和/或更新蚀刻掩模的方法
公开(公告)号：US06806037B2
公开(公告)日：2004-10-19
申请号：US10167785
申请日：2002-06-12
申请人： Matthias Goldbach , Thomas Hecht , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Bernhard Sell
IPC分类号： G03F726
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3085
摘要： An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.
摘要翻译：制造用于通过曝光的光致抗蚀剂层蚀刻基板的蚀刻掩模，使得暴露一次的区域尚未完全曝光，并且基于位于光致抗蚀剂层下方的反射层，额外暴露的区域完全暴露。因此，用于蚀刻衬底的第一蚀刻掩模可以通过第二蚀刻掩模来更新，因为施加到第一蚀刻掩模或代替第一蚀刻掩模的光致抗蚀剂层被暴露，使得已经被曝光一次还未完全曝光，并且基于位于光致抗蚀剂层下方并对应于第一蚀刻掩模的反射层另外暴露的区域被完全暴露。

3. 发明授权

US06674113B2 Trench capacitor and method for manufacturing the same 有权
标题翻译：沟槽电容器及其制造方法
公开(公告)号：US06674113B2
公开(公告)日：2004-01-06
申请号：US10254692
申请日：2002-09-25
申请人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
IPC分类号： H01L2708
CPC分类号： H01L27/10861
摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.
摘要翻译：沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。第一电容器电极具有延伸到基板中的管状结构。第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置之间。

4. 发明授权

US07199414B2 Stress-reduced layer system for use in storage capacitors 失效
标题翻译：用于存储电容器的应力降低层系统
公开(公告)号：US07199414B2
公开(公告)日：2007-04-03
申请号：US10780075
申请日：2004-02-17
申请人： Matthias Goldbach , Bernhard Sell , Annette Sänger
发明人： Matthias Goldbach , Bernhard Sell , Annette Sänger
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087 , H01L27/10852 , H01L27/10861
摘要： The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.
摘要翻译：应力降低层系统具有至少一个第一层多晶或单晶半导体材料，其邻接微晶或非晶，导电或绝缘的第二层。半导体层掺杂有至少两种相同导电类型的掺杂剂，其中至少一种适用于降低界面处的机械应力。在另一实施例中，应力降低层系统具有至少一个第一半导体材料层，导电或绝缘材料以及至少一个导电或绝缘的第二层。掺杂有至少一种适合于在第二层和第一层之间的界面处降低机械应力的掺杂剂的另一半导体层被布置在第一层和第二层之间，或者被施加到与界面相对的第一层或第二层。

5. 发明授权

US07009900B2 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell 失效
标题翻译：用于读出，评估和再次读取电荷状态到存储单元中的电路布置
公开(公告)号：US07009900B2
公开(公告)日：2006-03-07
申请号：US10944536
申请日：2004-09-17
申请人： Matthias Goldbach , Bernhard Sell
发明人： Matthias Goldbach , Bernhard Sell
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/41 , G11C29/12 , G11C29/38 , G11C29/50
摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).
摘要翻译：电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。

6. 发明申请

US20050099879A1 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell 失效
标题翻译：用于读出，评估和再次读取电荷状态到存储单元中的电路布置
公开(公告)号：US20050099879A1
公开(公告)日：2005-05-12
申请号：US10944536
申请日：2004-09-17
申请人： Matthias Goldbach , Bernhard Sell
发明人： Matthias Goldbach , Bernhard Sell
IPC分类号： G11C7/06 , G11C11/4091 , G11C29/12 , G11C29/38 , G11C29/50 , G11C8/02
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/41 , G11C29/12 , G11C29/38 , G11C29/50
摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).
摘要翻译：电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。

7. 发明授权

US06620724B1 Low resistivity deep trench fill for DRAM and EDRAM applications 有权
标题翻译：用于DRAM和EDRAM应用的低电阻深沟槽填充
公开(公告)号：US06620724B1
公开(公告)日：2003-09-16
申请号：US10142518
申请日：2002-05-09
申请人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
发明人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
IPC分类号： H01L214763
CPC分类号： H01L28/60 , H01L27/10861
摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.
摘要翻译：提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

8. 发明授权

US06960524B2 Method for production of a metallic or metal-containing layer 失效
标题翻译：金属或含金属层的制造方法
公开(公告)号：US06960524B2
公开(公告)日：2005-11-01
申请号：US10692150
申请日：2003-10-21
申请人： Thomas Hecht , Bernhard Sell , Annette Saenger
发明人： Thomas Hecht , Bernhard Sell , Annette Saenger
IPC分类号： C23C16/02 , H01L21/02 , H01L21/28 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/44
CPC分类号： H01L21/28194 , C23C16/0272 , H01L21/28079 , H01L21/28211 , H01L21/28518 , H01L21/3141 , H01L21/31645 , H01L21/76802 , H01L21/76831 , H01L28/60 , H01L29/495 , H01L29/513 , H01L29/517
摘要： The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.
摘要翻译：本发明涉及一种通过在含锗层或含锗层上使用前体来制造金属或含金属层（5）的方法，特别是电子元件，由此施加中间层到使用前的硅或锗含量层。所述中间层至少形成了用于蚀刻含硅或含锗层的元素或前体的扩散阻挡层，并且本身对前蚀刻的蚀刻本身具有抗蚀性。

9. 发明授权

US06835417B2 Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes 有权
标题翻译：用于通过ALD / CVD工艺与快速热处理结合沉积薄层的方法和装置
公开(公告)号：US06835417B2
公开(公告)日：2004-12-28
申请号：US10375529
申请日：2003-02-27
申请人： Annette Saenger , Bernhard Sell , Harald Seidl , Thomas Hecht , Martin Gutsche
发明人： Annette Saenger , Bernhard Sell , Harald Seidl , Thomas Hecht , Martin Gutsche
IPC分类号： C23C1600
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/40 , C23C16/42 , C23C16/45544 , C23C16/46 , C23C16/481
摘要： The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.
摘要翻译： ALD处理室具有加热辐射源，并且工艺顺序包括在布置在ALD处理室中的衬底的衬底表面上的快速温度变化。控制温度变化，并通过原位温度步骤优化ALD和CVD工艺，例如为了生产纳米级氨基酸。

10. 发明授权

US08941214B2 Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width 有权
标题翻译：具有颈缩半导体本体的半导体器件和形成宽度不同的半导体器件的方法
公开(公告)号：US08941214B2
公开(公告)日：2015-01-27
申请号：US13995634
申请日：2011-12-22
申请人： Bernhard Sell
发明人： Bernhard Sell
IPC分类号： H01L29/06 , H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/02532 , H01L21/30604 , H01L21/3083 , H01L21/823412 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/16 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/6681 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
摘要翻译：描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。例如，半导体器件包括设置在衬底上方的半导体本体。栅电极堆叠设置在半导体本体的一部分上，以在栅电极堆叠下方限定半导体本体中的沟道区。源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

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