会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 8. 发明授权
    • Notched trailing shield for perpendicular write head
    • 用于垂直写头的缺口拖尾屏蔽
    • US07296337B2
    • 2007-11-20
    • US10853805
    • 2004-05-25
    • Ian Robson McFadyen
    • Ian Robson McFadyen
    • G11B5/127H04R31/00
    • G11B5/1278Y10T29/49043Y10T29/49046Y10T29/49048Y10T29/49052
    • During fabrication of a perpendicular write head in a wafer, at least two sides of a write pole are defined (e.g. by ion milling) while a third side of the write pole is protected by a masking material. At this stage, a material that is to be located in the write gap is already present between the write pole and the masking material. After definition of the write pole surfaces, a layer of dielectric material is deposited. During this deposition, the masking material is still present. Thereafter, the masking material (and any dielectric material thereon) is removed, to form a hole in the dielectric material. Next, a trailing shield is formed in the structure, so that at least one portion of the trailing shield is located in the hole, and another portion of the trailing shield is located over the dielectric material, in an area adjacent to the hole. Note that the gap material is now sandwiched between the portion of the trailing shield in the hole, and the write pole.
    • 在制造晶片中的垂直写头时,写极的至少两侧被限定(例如通过离子铣削),而写极的第三侧由掩模材料保护。 在该阶段,位于写入间隙中的材料已经存在于写入极和掩模材料之间。 在写入磁极表面的定义之后,沉积介电材料层。 在该沉积期间,掩模材料仍然存在。 此后,去除掩模材料(及其上的任何介电材料),以在电介质材料中形成孔。 接下来,在该结构中形成尾部屏蔽,使得后屏蔽件的至少一部分位于孔中,并且后屏蔽件的另一部分位于电介质材料上方,邻近该孔。 注意,间隙材料现在夹在孔中的后屏蔽的部分和写极之间。
    • 9. 发明授权
    • Device and method of reducing ESD damage in thin film read heads which enables measurement of gap resistances and method of making
    • 减薄薄膜读取头中的ESD损伤的装置和方法,能够测量间隙电阻和制作方法
    • US06678127B2
    • 2004-01-13
    • US09753804
    • 2001-01-02
    • Richard HsiaoJames D. JarrattEmo Hilbrand KlaassenIan Robson McFadyenTimothy J. Moran
    • Richard HsiaoJames D. JarrattEmo Hilbrand KlaassenIan Robson McFadyenTimothy J. Moran
    • G11B540
    • B82Y10/00G11B5/33G11B5/3967G11B5/40G11B5/455G11B33/10G11B2005/0013Y10T29/49032Y10T29/49036Y10T29/49039Y10T29/49043Y10T29/49044Y10T29/49071Y10T29/49073Y10T29/49078
    • A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together. A test instrument is then employed for determining the combined parallel resistance of the resistors RS1 and RS2 by having a first side of the test instrument connected to the first node and the second side connected to each of the first and second shield layers. In the second embodiment a third resistor RS3 is connected between the second node and one of the shield layers, such as the second shield layer. The test instrument can determine the resistances of the first and second gap layers separately by being connected between the first node and the first shield layer for the resistance of the first gap layer or between the first node and the second shield layer for the resistance of the second gap layer.
    • 第一读取间隙层在第一屏蔽层和读取头的第一和第二引线层中的一个之间具有电阻RG1,并且第二读取间隙层在第二屏蔽层和第一和第二引线之间的电阻RG2 读头的引导层。 通过第一节点和第一和第二屏蔽层中的每一个之间的多个电阻器提供连接,其中多个电阻器至少包括第一和第二电阻器RS1和RS2,并且第一节点连接到第一和第二屏蔽层中的所述第一和第二屏蔽层 第二铅层。 第二节点位于第一和第二电阻器RS1和RS2之间。 运算放大器具有分别连接到第一和第二节点的第一和第二输入,以跨过第一电阻器RS1并且具有连接到第一节点的输出,用于将第一和第二节点维持在共同的电压电位。 在第一实施例中,第一和第二屏蔽层被短路在一起。 然后通过使测试仪器的第一侧连接到第一节点并且第二侧连接到第一和第二屏蔽层中的每一个,然后采用测试仪器来确定电阻器RS1和RS2的组合并联电阻。 在第二实施例中,第三电阻器RS3连接在第二节点和其中一个屏蔽层之间,例如第二屏蔽层。 测试仪器可以通过连接在第一节点和第一屏蔽层之间来分别确定第一和第二间隙层的电阻,用于第一间隙层的电阻或第一节点和第二屏蔽层之间的电阻, 第二间隙层。