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    • 3. 发明授权
    • Method and materials for patterning a neutral surface
    • 用于图案化中性面的方法和材料
    • US07790350B2
    • 2010-09-07
    • US11882163
    • 2007-07-30
    • Gregory BreytaMatthew E. Colburn
    • Gregory BreytaMatthew E. Colburn
    • G03F7/00G03F7/004
    • H01L21/31144B82Y10/00H01L21/7682
    • A self assembly step for the manufacture of an electronic component comprising, e.g., a semiconductor chip or semiconductor array or wafer comprises forming a block copolymer film placed on a random copolymer film substrate operatively associated with the electronic component and the block copolymer film wherein the surface energy of the random copolymer film is tailored by use of a photolithographic or chemical process prior to the self assembly step. By prior deterministic control over regional surface properties of the random copolymer film, domains of the block copolymer film form only in predefined areas. This approach offers simplified processing and a precise control of regions where domain formation occurs. Selective removal of some of the domains allows for further processing of the electronic component.
    • 用于制造包括例如半导体芯片或半导体阵列或晶片的电子部件的自组装步骤包括形成位于与电子部件和嵌段共聚物膜操作相关的无规共聚物膜基材上的嵌段共聚物膜,其中表面 在自组装步骤之前,通过使用光刻或化学方法来调整无规共聚物膜的能量。 通过对无规共聚物膜的区域表面性质的先前确定性控制,嵌段共聚物膜的畴仅形成在预定区域中。 这种方法提供简化的处理和精确控制域形成发生的区域。 某些域的选择性删除允许进一步处理电子元件。
    • 5. 发明申请
    • Method and materials for patterning a neutral surface
    • 用于图案化中性面的方法和材料
    • US20090035668A1
    • 2009-02-05
    • US11882163
    • 2007-07-30
    • Gregory BreytaMatthew E. Colburn
    • Gregory BreytaMatthew E. Colburn
    • G03C5/00
    • H01L21/31144B82Y10/00H01L21/7682
    • A self assembly step for the manufacture of an electronic component comprising, e.g., a semiconductor chip or semiconductor array or wafer comprises forming a diblock copolymer film placed on a random copolymer film substrate operatively associated with the electronic component and the diblock copolymer film wherein the surface energy of the random copolymer film is tailored by use of a photolithographic process prior to the self assembly step. By prior deterministic control over regional surface properties of the random copolymer film, domains of the diblock copolymer film form only in predefined areas. This approach offers simplified processing and a precise control of regions where domain formation occurs. Selective removal of some of the domains allows for further processing of the electronic component.
    • 用于制造包括例如半导体芯片或半导体阵列或晶片的电子部件的自组装步骤包括形成放置在与电子部件和二嵌段共聚物膜操作相关的无规共聚物膜基材上的二嵌段共聚物膜,其中表面 在自组装步骤之前通过使用光刻工艺来调整无规共聚物膜的能量。 通过对无规共聚物膜的区域表面性质的先前确定性控制,二嵌段共聚物膜的畴仅形成在预定区域中。 这种方法提供简化的处理和精确控制域形成发生的区域。 某些域的选择性删除允许进一步处理电子元件。
    • 10. 发明授权
    • Chemical trim of photoresist lines by means of a tuned overcoat
    • 通过调整的外涂层对光致抗蚀剂线进行化学修饰
    • US08137893B2
    • 2012-03-20
    • US12983297
    • 2011-01-01
    • Sean David BurnsMatthew E. ColburnSteven John HolmesWu-Song Huang
    • Sean David BurnsMatthew E. ColburnSteven John HolmesWu-Song Huang
    • G03F7/00G03F7/004G03F7/40
    • G03F7/40Y10T428/24802
    • A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line. The invention also comprises a product produced by this process.
    • 新的光刻工艺包括在保持光刻工艺窗口的同时降低图像的线宽,并且使用该工艺来制造包括nm阶(例如约22nm)的节点半导体器件的间距分裂结构。 该方法包括在基片的表面上施加平版印刷抗蚀剂层,并对平版印刷抗蚀剂层进行图形化和显影,以形成具有初始线宽的nm阶节点图像。 用酸性聚合物覆盖nm阶节点图像产生酸性聚合物涂层图像。 加热酸性聚合物涂覆的图像给图像上的热处理涂层,加热在足以将初始线宽降低到随后变窄的线宽的温度和时间内进行。 显影加热处理的涂层将其从图像中去除,从而在基底上产生独立的修整光刻特征。 可选地,重复前述步骤进一步减小了变窄线的线宽。 本发明还包括通过该方法生产的产品。