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1. 发明授权

US5081607A Arithmetic logic unit 失效
标题翻译：算术逻辑单元
公开(公告)号：US5081607A
公开(公告)日：1992-01-14
申请号：US483859
申请日：1990-02-23
申请人： Matthew D. Bates , Nicholas D. Butler , Adrian C. Gay , Jong H. Kim , Roderick M. West
发明人： Matthew D. Bates , Nicholas D. Butler , Adrian C. Gay , Jong H. Kim , Roderick M. West
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506 , G06T1/20
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.

2. 发明授权

US5210723A Memory with page mode 失效
标题翻译：内存与页面模式
公开(公告)号：US5210723A
公开(公告)日：1993-05-11
申请号：US606262
申请日：1990-10-31
申请人： Matthew D. Bates , Adrian C. Gay , Roderick M. West , Todd Williams
发明人： Matthew D. Bates , Adrian C. Gay , Roderick M. West , Todd Williams
IPC分类号： G11C7/10 , G11C8/12
CPC分类号： G11C8/12 , G11C7/1015 , G11C7/1021
摘要： In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.
摘要翻译：在可通过行和列寻址并且以页面模式操作的存储器中，在单个行周期内执行多个列周期，提供了用于对所选列周期的行地址进行步进的布置，从而可以在存储器地址中提供持续的页面模式操作空间。优选地，当列地址选通变为有效时响应于提供的行改变信号而发生步进，并且当行地址选通变为有效时由提供的模式信号确定步进方向。采用内存分段来促进多行的同时激活和恢复。

3. 发明授权

US08184663B2 Multi-format stream re-multiplexer for multi-pass, multi-stream, multiplexed transport stream processing 有权
标题翻译：用于多通道，多流，多路传输流处理的多格式流多路复用器
公开(公告)号：US08184663B2
公开(公告)日：2012-05-22
申请号：US12145288
申请日：2008-06-24
申请人： Matthew D. Bates , Steven B. Ehlers
发明人： Matthew D. Bates , Steven B. Ehlers
IPC分类号： H04J3/04 , H04J3/24
CPC分类号： H04N21/4147 , H04N21/4344 , H04N21/4405 , H04N21/4408
摘要： A device for transport stream processing is provided. The device includes a plurality of data inputs and a transport stream re-multiplexer for receiving a plurality of data streams from the plurality of data stream inputs and multiplexing the data streams into a transport stream. A transport stream processor receives the transport stream, de-multiplexes the transport stream to process one or more of the data streams, and provides the processed data stream to the transport stream re-multiplexer as one of the plurality of data streams.
摘要翻译：提供了一种用于传输流处理的设备。该装置包括多个数据输入和传输流再多路复用器，用于从多个数据流输入端接收多个数据流，并将数据流复用成传输流。传输流处理器接收传输流，对传输流进行解复用以处理一个或多个数据流，并将经处理的数据流作为多个数据流之一提供给传输流再多路复用器。

4. 发明申请

US20080317118A1 Multi-Format Stream Re-Multiplexer for Multi-Pass, Multi-Stream, Multiplexed Transport Stream Processing 有权
标题翻译：用于多通道，多流，多路复用传输流处理的多格式流重新复用器
公开(公告)号：US20080317118A1
公开(公告)日：2008-12-25
申请号：US12145288
申请日：2008-06-24
申请人： Matthew D. Bates , Steven B. Ehlers
发明人： Matthew D. Bates , Steven B. Ehlers
IPC分类号： H04B1/66
CPC分类号： H04N21/4147 , H04N21/4344 , H04N21/4405 , H04N21/4408
摘要： A device for transport stream processing is provided. The device includes a plurality of data inputs and a transport stream re-multiplexer for receiving a plurality of data streams from the plurality of data stream inputs and multiplexing the data streams into a transport stream. A transport stream processor receives the transport stream, de-multiplexes the transport stream to process one or more of the data streams, and provides the processed data stream to the transport stream re-multiplexer as one of the plurality of data streams.
摘要翻译：提供了一种用于传输流处理的设备。该装置包括多个数据输入和传输流再多路复用器，用于从多个数据流输入端接收多个数据流，并将数据流复用成传输流。传输流处理器接收传输流，对传输流进行解复用以处理一个或多个数据流，并将经处理的数据流作为多个数据流之一提供给传输流再多路复用器。

5. 发明授权

US5631672A Self-timed real-time data transfer in video-RAM 失效
标题翻译：在视频RAM中自定时实时数据传输
公开(公告)号：US5631672A
公开(公告)日：1997-05-20
申请号：US499557
申请日：1995-07-07
申请人： Matthew D. Bates , Roderick M. P. West
发明人： Matthew D. Bates , Roderick M. P. West
IPC分类号： G09G5/00 , G09G5/395 , G11C7/10 , G11C11/401
CPC分类号： G09G5/395 , G11C7/1075
摘要： A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.
摘要翻译：一种由具有用于输入行，列和目标地址的地址输入的RAM陆军和具有串行输出端口的串行访问阵列组成的视频RAM半导体存储器件。视频RAM具有地址/控制逻辑，其检测来自外部控制器的诸如RAS时钟的激励，指示用于RAM阵列和串行访问阵列之间的数据传输的粗略定时位置。然后，控制逻辑提供与串行时钟在内部同步的控制信号，并且在分针指针等于小于可编程目标值或输入目标地址的值的周期期间发生。这使得RAM阵列中对应于输入行地址的一行在RAM阵列和串行存取阵列之间传输。

6. 发明申请

US20080317249A1 Encoded Digital Video Content Protection Between Transport Demultiplexer and Decoder 有权
标题翻译：传输解复用器和解码器之间的编码数字视频内容保护
公开(公告)号：US20080317249A1
公开(公告)日：2008-12-25
申请号：US12144319
申请日：2008-06-23
申请人： Matthew D. Bates , Lance G. Hehenberger
发明人： Matthew D. Bates , Lance G. Hehenberger
IPC分类号： H04L9/00
CPC分类号： H04L9/0869 , H04L2209/56 , H04L2209/60
摘要： A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.
摘要翻译：提供了一种用于加密和解密数据的系统。该系统包括用于接收数据分组的客户端，设置密码比特的值，以及通过系统总线发送数据分组。加密模块从系统总线接收数据分组，并根据加密比特的第一值对数据分组执行密码学功能。存储器控制器从系统总线接收数据包，并且基于密码比特的第二值在数据包上执行非密码学功能。

7. 发明授权

US08064600B2 Encoded digital video content protection between transport demultiplexer and decoder 有权
标题翻译：传输解复用器和解码器之间的编码数字视频内容保护
公开(公告)号：US08064600B2
公开(公告)日：2011-11-22
申请号：US12144319
申请日：2008-06-23
申请人： Matthew D. Bates , Lance G. Hehenberger
发明人： Matthew D. Bates , Lance G. Hehenberger
IPC分类号： H04K1/00
CPC分类号： H04L9/0869 , H04L2209/56 , H04L2209/60
摘要： A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.
摘要翻译：提供了一种用于加密和解密数据的系统。该系统包括用于接收数据分组的客户端，设置密码比特的值，以及通过系统总线发送数据分组。加密模块从系统总线接收数据分组，并根据加密比特的第一值对数据分组执行密码学功能。存储器控制器从系统总线接收数据包，并且基于密码比特的第二值在数据包上执行非密码学功能。

8. 发明授权

US5940610A Using prioritized interrupt callback routines to process different types of multimedia information 失效
标题翻译：使用优先级中断回调例程处理不同类型的多媒体信息
公开(公告)号：US5940610A
公开(公告)日：1999-08-17
申请号：US720891
申请日：1996-10-03
申请人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
发明人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
IPC分类号： G09G5/02 , G09G5/08 , G09G5/36 , G09G5/395 , H04N5/44 , G06F13/00
CPC分类号： G09G5/363 , G09G5/08 , G09G5/395 , G09G2340/125 , G09G5/02 , H04N5/4401
摘要： Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e.g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e.g. at a single level) to provide priorities based upon the type of interrupt cause or media. Each interrupt cause activates only the appropriate callback functions. Two different virtual machine sessions (e.g. Windows, DOS) share an interrupt line to process interrupt requests form one (1) session (e.g. Windows) before processing interrupt requests from the other.
摘要翻译：多媒体信息（例如，图形，视频，声音，控制信息）根据CPU命令从CPU主存储器传递到显示存储器。该信息可以用识别不同媒体的相关联的分组类型来分组。媒体流控制器处理信息并将处理的信息传递到显示存储器。媒体流控制器中的控制器将多媒体信息单独传递到显示存储器。媒体流控制器中的PACDAC控制器使显示存储器中的媒体（例如，图形，视频）被传送到PACDAC进行显示。该传输的格式，顺序和速率可以由软件在逐帧的基础上灵活地控制。仲裁逻辑为媒体流控制器中的不同控制器确定优先级，因此它们可以共享用于访问显示存储器的单个总线。单个中断控制器协调中断（例如在单个级别），以根据中断原因或介质的类型提供优先级。每个中断原因仅激活适当的回调函数。在处理来自另一个的中断请求之前，两个不同的虚拟机会话（例如Windows，DOS）共享中断线来处理从一（1）个会话（例如Windows）的中断请求。

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