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1. 发明申请

US20050079719A1 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US20050079719A1
公开(公告)日：2005-04-14
申请号：US10683333
申请日：2003-10-10
申请人： Matthew Colburn , Satya Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew Colburn , Satya Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L23/52 , H05K3/10 , H05K3/46
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

2. 发明授权

US07268432B2 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US07268432B2
公开(公告)日：2007-09-11
申请号：US10683333
申请日：2003-10-10
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

3. 发明申请

US20120261823A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 有权
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20120261823A1
公开(公告)日：2012-10-18
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

4. 发明授权

US08358011B1 Interconnect structures with engineered dielectrics with nanocolumnar porosity 失效
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08358011B1
公开(公告)日：2013-01-22
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

5. 发明申请

US20130009315A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 失效
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20130009315A1
公开(公告)日：2013-01-10
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

6. 发明授权

US08901741B2 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08901741B2
公开(公告)日：2014-12-02
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

7. 发明申请

US20060163646A1 Nonvolatile memory device using semiconductor nanocrystals and method of forming same 有权
公开(公告)号：US20060163646A1
公开(公告)日：2006-07-27
申请号：US11373127
申请日：2006-03-13
申请人： Charles Black , Kathryn Guarini
发明人： Charles Black , Kathryn Guarini
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , B82Y10/00 , G11C2216/06 , H01L21/02118 , H01L21/02227 , H01L21/02532 , H01L21/02636 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L29/42332 , H01L29/7887 , H01L29/7923 , Y10S438/947 , Y10S977/78 , Y10S977/783 , Y10S977/813 , Y10S977/856 , Y10S977/883 , Y10S977/888 , Y10S977/893
摘要： A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

8. 发明授权

US07354059B2 Wheelbarrow stand with tilt leveling mechanism 有权
标题翻译：独轮车站立与倾斜调平机构
公开(公告)号：US07354059B2
公开(公告)日：2008-04-08
申请号：US11136290
申请日：2005-05-24
申请人： Charles Black
发明人： Charles Black
IPC分类号： B61B1/18
CPC分类号： B62B1/24
摘要： A tilting mechanism incorporated into a conventional load carrying device including a bucket portion, a pair of elongated handles supporting the bucket portion, and a front wheel. The tilting mechanism includes a frame adapted to being secured to a rearwardly extending location of the elongated handles and such that the bucket portion is disposed between the frame and the front wheel. Elongated supports are incorporated into the frame and, in combination with the front wheel, support the wheelbarrow upon a surface. The frame includes structure for establishing an angle or incline, relative to an uneven or peaked surface, and is actuated to facilitate tilting of the bucket portion about a longitudinal axis extending through the load carrying device.
摘要翻译：一种结合到传统的承载装置中的倾斜机构，包括铲斗部分，一对支撑铲斗部分的细长把手和前轮。倾斜机构包括适于固定到细长把手的向后延伸位置并且使得铲斗部分设置在框架和前轮之间的框架。延长的支撑件被结合到框架中，并且与前轮组合在一个表面上支撑独轮车。框架包括相对于不平坦或峰值表面建立角度或倾斜的结构，并且被致动以便于围绕延伸穿过承载装置的纵向轴线倾斜铲斗部分。

9. 发明授权

US06506660B2 Semiconductor with nanoscale features 失效
标题翻译：半导体具有纳米级特征
公开(公告)号：US06506660B2
公开(公告)日：2003-01-14
申请号：US10008092
申请日：2001-11-13
申请人： Steven J. Holmes , Charles Black , David J. Frank , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William Hsioh-Lien Ma , Keith R. Milkove , Kathryn W. Guarini
发明人： Steven J. Holmes , Charles Black , David J. Frank , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William Hsioh-Lien Ma , Keith R. Milkove , Kathryn W. Guarini
IPC分类号： H01L2120
CPC分类号： H01L28/92
摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.
摘要翻译：描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征，所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容电极图案。

10. 发明申请

US20070256480A1 SCANNING PROBE MICROSCOPY TIPS COMPOSED OF NANOPARTICLES AND METHODS TO FORM SAME 审中-公开
标题翻译：扫描探针组成的纳米微粒及其形成方法
公开(公告)号：US20070256480A1
公开(公告)日：2007-11-08
申请号：US11775316
申请日：2007-07-10
申请人： Charles Black , Adam Cohen , Christopher Murray , Robert Sandstrom
发明人： Charles Black , Adam Cohen , Christopher Murray , Robert Sandstrom
IPC分类号： G01B5/28
CPC分类号： G01Q70/16 , G01Q70/14 , Y10S977/924 , Y10T428/254
摘要： A structure and method for improving the spatial resolution of a scanning probe microscope (SPM) tip, which has been coated with a layer of chemically-synthesized nanoparticles. The nanoparticles are either single-species or heterogeneous, such that the single-species nanoparticles can be either ferromagnetic, paramagnetic, superparamagnetic, antiferromagnetic, ferrimagnetic, magneto-optic, ferroelectric, piezoelectric, superconducting, semiconducting, magnetically-doped semiconducting, insulating, fluorescent, or chemically catalytic. The layer of nanoparticles is at least two nanoparticles thick, or alternatively, is a single layer of nanoparticles thick, or alternatively, is a single layer of nanoparticles thick and covers only the tip apex portion of the tip, or alternatively, only a single nanoparticle is affixed to the tip apex. Alternatively, the layer of nanoparticles is transformed into an electrically-continuous magnetic film by annealing at a high temperature.
摘要翻译：用于改善扫描探针显微镜（SPM）尖端的空间分辨率的结构和方法，其已经涂覆有化学合成的纳米颗粒层。纳米颗粒是单种或非均质的，使得单种纳米颗粒可以是铁磁性，顺磁性，超顺磁性，反铁磁性，亚铁磁性，磁光学，铁电体，压电，超导，半导体，磁掺杂半导体，绝缘，荧光，或化学催化。纳米颗粒层是至少两个纳米颗粒厚度，或者可选地，是单层纳米颗粒的厚度，或者可选地，单层纳米颗粒是厚的，并且仅覆盖尖端的顶端部分，或者仅仅是单个纳米颗粒贴在尖端顶端。或者，通过在高温下退火将纳米颗粒层转变成电连续的磁性膜。

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