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1. 发明申请

US20100124823A1 NOVEL METHOD FOR REMOVING DUMMY POLY IN A GATE LAST PROCESS 有权
标题翻译：用于在门过程中去除多余聚合物的新方法
公开(公告)号：US20100124823A1
公开(公告)日：2010-05-20
申请号：US12275082
申请日：2008-11-20
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
IPC分类号： H01L21/302 , H01L21/71
CPC分类号： H01L21/32134 , H01L21/02071 , H01L21/28035 , H01L21/823828 , H01L21/82385 , H01L27/11 , H01L29/66583
摘要： A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
摘要翻译：提供了制造半导体器件的方法。该方法包括通过循环从位于衬底上的栅极结构去除硅材料，包括：蚀刻硅材料以除去其中的一部分，其中衬底以旋转速率纺丝，向衬底施加清洁剂，并干燥基材; 并重复该循环，其中随后的循环包括用于在蚀刻期间旋转衬底的随后旋转速率，并且其中随后的旋转速率不超过先前循环的旋转速率。

2. 发明授权

US08415254B2 Method for removing dummy poly in a gate last process 有权
标题翻译：在门最后一个过程中去除虚拟多边形的方法
公开(公告)号：US08415254B2
公开(公告)日：2013-04-09
申请号：US12275082
申请日：2008-11-20
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
IPC分类号： H01L21/302
CPC分类号： H01L21/32134 , H01L21/02071 , H01L21/28035 , H01L21/823828 , H01L21/82385 , H01L27/11 , H01L29/66583
摘要： A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
摘要翻译：提供了制造半导体器件的方法。该方法包括通过循环从位于衬底上的栅极结构去除硅材料，包括：蚀刻硅材料以除去其中的一部分，其中衬底以旋转速率纺丝，向衬底施加清洁剂，并干燥基材; 并重复该循环，其中随后的循环包括用于在蚀刻期间旋转衬底的随后旋转速率，并且其中随后的旋转速率不超过先前循环的旋转速率。

3. 发明授权

US08173504B2 Method of fabricating gate electrode using a treated hard mask 有权
标题翻译：使用经处理的硬掩模制造栅电极的方法
公开(公告)号：US08173504B2
公开(公告)日：2012-05-08
申请号：US12758491
申请日：2010-04-12
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Hui Ouyang , Chi-Ming Yang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Hui Ouyang , Chi-Ming Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/4916 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.
摘要翻译：公开了一种用于制造集成器件的方法。在基板上设置多晶硅栅电极层。在一个实施例中，在多晶硅栅极电极层上提供处理以在栅电极层中引入物质并在其中形成电中和部分。然后，将具有有限厚度的硬掩模层施加在经处理的多晶硅栅极电极层上。因此，在将硬掩模层和经处理的多晶硅栅电极图案化之后，在栅极结构上对基板进行倾斜角度离子注入。

4. 发明授权

US08268085B2 Methods for forming metal gate transistors 有权
标题翻译：形成金属栅晶体管的方法
公开(公告)号：US08268085B2
公开(公告)日：2012-09-18
申请号：US12719532
申请日：2010-03-08
申请人： Matt Yeh , Shun Wu Lin , Hui Ouyang
发明人： Matt Yeh , Shun Wu Lin , Hui Ouyang
IPC分类号： B08B3/04
CPC分类号： H01L21/02068 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.
摘要翻译：提供了一种在衬底上清洁金属栅极晶体管的栅极电介质上的扩散阻挡层的方法。该方法包括用包含至少一种表面活性剂的第一溶液清洗扩散阻挡层。第一溶液的表面活性剂的量约为临界胶束浓度（CMC）或更高。扩散阻挡层用第二种溶液清洗。第二种解决方案具有去除扩散阻挡层上的颗粒的物理力。第二溶液基本上不与扩散阻挡层相互作用。

5. 发明申请

US20100240204A1 METHODS FOR FORMING METAL GATE TRANSISTORS 有权
标题翻译：形成金属栅极晶体管的方法
公开(公告)号：US20100240204A1
公开(公告)日：2010-09-23
申请号：US12719532
申请日：2010-03-08
申请人： Matt YEH , Shun Wu Lin , Hui Ouyang
发明人： Matt YEH , Shun Wu Lin , Hui Ouyang
IPC分类号： H01L21/28 , H01L21/302 , B08B3/00
CPC分类号： H01L21/02068 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.
摘要翻译：提供了一种在衬底上清洁金属栅极晶体管的栅极电介质上的扩散阻挡层的方法。该方法包括用包含至少一种表面活性剂的第一溶液清洗扩散阻挡层。第一溶液的表面活性剂的量约为临界胶束浓度（CMC）或更高。扩散阻挡层用第二种溶液清洗。第二种解决方案具有去除扩散阻挡层上的颗粒的物理力。第二溶液基本上不与扩散阻挡层相互作用。

6. 发明申请

US20100112811A1 METHOD FOR PATTERNING A METAL GATE 有权
标题翻译：用于绘制金属门的方法
公开(公告)号：US20100112811A1
公开(公告)日：2010-05-06
申请号：US12431838
申请日：2009-04-29
申请人： Matt Yeh , Shun Wu Lin , Chung-Ming Wang , Chi-Chun Chen
发明人： Matt Yeh , Shun Wu Lin , Chung-Ming Wang , Chi-Chun Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/823828 , H01L21/82385 , H01L27/0207 , H01L29/66545
摘要： The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.
摘要翻译：本公开提供了一种用于制造半导体器件的方法。该方法包括在半导体衬底上形成第一，第二，第三和第四栅极结构，每个栅极结构具有虚拟栅极，从第一，第二，第三和第四栅极结构去除伪栅极，从而形成第一，第三沟槽和第四沟槽，分别形成金属层以部分地填充在第一，第二，第三和第四沟槽中，在第一，第二和第三沟槽上形成第一光致抗蚀剂层，蚀刻金属层的一部分第四沟槽，去除第一光致抗蚀剂层，在第二和第三沟槽上形成第二光致抗蚀剂层，蚀刻第一沟槽中的金属层和第四沟槽中金属层的剩余部分，以及去除第二光致抗蚀剂层。

7. 发明申请

US20100048011A1 METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE 有权
标题翻译：图案化半导体器件金属栅的方法
公开(公告)号：US20100048011A1
公开(公告)日：2010-02-25
申请号：US12371672
申请日：2009-02-16
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28105 , H01L21/28123 , H01L21/28158 , H01L21/31111 , H01L21/32139 , H01L29/401
摘要： Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
摘要翻译：提供了包括高k栅极电介质的金属栅极结构的图案化方法。在一个实施方案中，可以使用可溶性硬掩模层来提供掩模元件以对金属栅极进行图案化。可溶性硬掩模层可以通过水或光致抗蚀剂显影剂从基底上去除。在一个实施例中，形成包括高k电介质的硬掩模。在另一个实施例中，保护层形成在光致抗蚀剂图案下面。保护层可以保护形成在衬底上的一个或多个层与光致抗蚀剂剥离工艺。

8. 发明授权

US07732344B1 High selectivity etching process for metal gate N/P patterning 失效
标题翻译：金属栅N / P图案化的高选择性蚀刻工艺
公开(公告)号：US07732344B1
公开(公告)日：2010-06-08
申请号：US12478922
申请日：2009-06-05
申请人： Fang Wen Tsai , Matt Yeh , Ming-Jun Wang , Shun Wu Lin , Chi-Chun Chen , Zin-Chang Wei , Chyi-Shyuan Chern
发明人： Fang Wen Tsai , Matt Yeh , Ming-Jun Wang , Shun Wu Lin , Chi-Chun Chen , Zin-Chang Wei , Chyi-Shyuan Chern
IPC分类号： H01L21/302
CPC分类号： H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , Y10S438/942
摘要： A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
摘要翻译：公开了一种制造具有改进性能的集成电路的方法。该方法包括提供基底; 在衬底上形成硬掩模层; 形成硬掩模层的受保护部分和未保护部分; 对硬掩模层的未保护部分进行第一蚀刻工艺，第二蚀刻工艺和第三蚀刻工艺，其中第一蚀刻工艺部分地去除硬掩模层的未保护部分，第二蚀刻工艺处理未保护部分的硬掩模层，并且第三蚀刻工艺除去硬掩模层的剩余的未保护部分; 以及执行第四蚀刻工艺以去除所述硬掩模层的被保护部分。

9. 发明授权

US07727900B2 Surface preparation for gate oxide formation that avoids chemical oxide formation 有权
标题翻译：防止化学氧化物形成的栅极氧化物形成的表面处理
公开(公告)号：US07727900B2
公开(公告)日：2010-06-01
申请号：US11358624
申请日：2006-02-21
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/28167 , H01L21/31133 , H01L21/823462
摘要： A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.
摘要翻译：可用于半导体制造的清洁顺序有效地清洁半导体衬底，同时防止其上形成化学氧化物。该序列包括以下顺序：1）用HF溶液处理; 2）用纯H 2 SO 4处理; 3）用H 2 O 2溶液处理; 4）去离子水冲洗; 和5）用HCl溶液处理。纯H 2 SO 4溶液可以包括约百分之九十八（98％）或更高的H 2 SO 4浓度。在HCl溶液处理之后，清洁的表面可以是不含厚度为5埃或更大的化学氧化物的硅表面。本发明在利用多个栅极氧化物厚度的半导体器件中具有特别的优点。

10. 发明授权

US08357617B2 Method of patterning a metal gate of semiconductor device 有权
公开(公告)号：US08357617B2
公开(公告)日：2013-01-22
申请号：US12371672
申请日：2009-02-16
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
IPC分类号： H01L21/302
CPC分类号： H01L21/28105 , H01L21/28123 , H01L21/28158 , H01L21/31111 , H01L21/32139 , H01L29/401
摘要： Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

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