专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012002994A1 SELECTIVE EPITAXY OF SI-CONTAINING MATERIALS AND SUBSTITUTIONALLY DOPED CRYSTALLINE SI-CONTAINING MATERIALS 审中-公开
标题翻译：含SI材料的选择性外延和替代掺杂的含晶体材料
公开(公告)号：WO2012002994A1
公开(公告)日：2012-01-05
申请号：PCT/US2011/001116
申请日：2011-06-23
申请人： MATHESON TRI-GAS, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION , FRANCIS, Terry, Arthur , HASAKA, Satoshi , BRABANT, Paul, David , TORRES, Robert, Jr. , HE, Hong , REZNICEK, Alexander , ADAM, Thomas, N. , SADANA, Devendra, K.
发明人： FRANCIS, Terry, Arthur , HASAKA, Satoshi , BRABANT, Paul, David , TORRES, Robert, Jr. , HE, Hong , REZNICEK, Alexander , ADAM, Thomas, N. , SADANA, Devendra, K.
IPC分类号： C30B25/02
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550°C and a pressure in the range of about 10 mTorr - 200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.
摘要翻译：本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速小于约550℃，压力范围为约10mTorr-200Torr。此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳。

2. 发明公开

EP2588650A1 SELECTIVE EPITAXY OF SI-CONTAINING MATERIALS AND SUBSTITUTIONALLY DOPED CRYSTALLINE SI-CONTAINING MATERIALS 审中-公开
标题翻译：选择性外延含Si材料和替代掺杂含Si的晶体材料
公开(公告)号：EP2588650A1
公开(公告)日：2013-05-08
申请号：EP11801264.0
申请日：2011-06-23
申请人： Matheson Tri-Gas, Inc. , International Business Machines Corporation
发明人： FRANCIS, Terry, Arthur , HASAKA, Satoshi , BRABANT, Paul, David , TORRES, Robert, Jr. , HE, Hong , REZNICEK, Alexander , ADAM, Thomas, N. , SADANA, Devendra, K.
IPC分类号： C30B25/02
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550°C and a pressure in the range of about 10 mTorr - 200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.

3. 发明申请

WO2013192119A1 EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM 审中-公开
标题翻译：平滑和高应变的德国的外源生长
公开(公告)号：WO2013192119A1
公开(公告)日：2013-12-27
申请号：PCT/US2013/046210
申请日：2013-06-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： REZNICEK, Alexander , ADAM, Thomas, N. , BEDELL, Stephen, W. , FOGEL, Keith, E. , SADANA, Devendra, K.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/20
CPC分类号： H01L29/165 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L29/1054 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group lll-V material on a silicon substrate.
摘要翻译：可以在约350℃的温度下，在磷化氢存在下将衬底暴露于锗前体，可直接在硅半导体衬底上生长的光滑的锗层。可以在有或没有SiGe种子层的情况下实现锗层形成。形成锗层的过程可以集成到标准CMOS处理中，以有效地形成体现薄的，高度应变的锗层的结构。这种结构可以实现处理灵活性。锗层还可以提供独特的物理性能，例如在光电子器件中，或者能够在硅衬底上形成III-VI族材料层。

4. 发明申请

WO2013158692A1 SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES 审中-公开
标题翻译：具有精细结构的半导体器件，以及形成具有结构的半导体器件的方法
公开(公告)号：WO2013158692A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036854
申请日：2013-04-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ADAM, Thomas, N. , CHENG, Kangguo , KHAKIFIROOZ, Ali , REZNICEK, Alexander
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/02532 , H01L21/0262 , H01L21/20 , H01L29/66477 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90° +/- 5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.
摘要翻译：一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ - 5°。外延半导体材料与至少两个翅片结构直接接触。

5. 发明申请

WO2013095879A1 THIN HETEROSTRUCTURE CHANNEL DEVICE 审中-公开
标题翻译：薄型结构通道设备
公开(公告)号：WO2013095879A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/066928
申请日：2012-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ADAM, Thomas, N. , CHENG, Kangguo , HE, Hong , KHAKIFIROOZ, Ali , REZNICEK, Alexander
IPC分类号： H01L21/331
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675°C to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

6. 发明申请

WO2014047258A1 SEMICONDUCTOR DEVICE AND METHOD WITH GREATER EPITAXIAL GROWTH ON 110 CRYSTAL PLANE 审中-公开
标题翻译：半导体器件和方法在110个晶体平面上具有更大的外延生长
公开(公告)号：WO2014047258A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/060569
申请日：2013-09-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ADAM, Thomas, N. , CHENG, Kangguo , HOLT, Judson Robert , TABAKMAN, Keith Howard , REZNICEK, Alexander
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： H01L21/20 , H01L21/02293 , H01L21/0243 , H01L21/02433 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor processing method is provided which promotes greater growth on crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on crystallographic planes and the least amount of growth occurs on crystallographic planes. The process can be applied to form embedded stressor regions 102 in planar field effect transistors 100, and the process can be used to grow semiconductor layers 107 207 on exposed wall surfaces 106 206 of adjacent fins 208 in source-drain regions 104 of finFETs to fill spaces between the fins 208.
摘要翻译：提供半导体处理方法，其促进在110晶体平面上比在其它晶体平面上更大的生长。与典型的外延生长过程相比，该方法的生长速率可以被逆转，使得在<110>晶面上发生最高生长速率，并且最小量的生长发生在晶体平面上。该方法可以应用于在平面场效应晶体管100中形成嵌入的应力区域102，并且该工艺可以用于在finFET的源极 - 漏极区域104中的相邻散热片208的暴露的壁表面106 206上生长半导体层107 207以填充翅片208之间的空间。

7. 发明申请

WO2013122776A1 HIGH PERFORMANCE MULTI-FINGER STRAINED SILICON GERMANIUM CHANNEL PFET AND METHOD OF FABRICATION 审中-公开
标题翻译：高性能多指纹应变硅锗通道PFET及其制造方法
公开(公告)号：WO2013122776A1
公开(公告)日：2013-08-22
申请号：PCT/US2013/024724
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： KHAKIFIROOZ, Ali , ADAM, Thomas, N. , CHENG, Kangguo , REZNICEK, Alexander
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/0642 , H01L29/0692 , H01L29/41783 , H01L29/4236 , H01L29/66575 , H01L29/66628
摘要： A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate.
摘要翻译：提供场效应晶体管及其制造方法。场效应晶体管包括设置在硅衬底上的多个细长的单轴应变SiGe区域，其定向成使得它们与通道中电载体的流动方向平行。细长的单轴应变SiGe区域垂直于晶体管栅极定向并穿过晶体管栅极。

8. 发明申请

WO2007025259A3 MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS 审中-公开
公开(公告)号：WO2007025259A3
公开(公告)日：2007-03-01
申请号：PCT/US2006/033582
申请日：2006-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , ADAM, Thomas, N.
发明人： CHIDAMBARRAO, Dureseti , ADAM, Thomas, N.
IPC分类号： H01L21/331 , H01L31/072
摘要： The present invention relates to a high performance heterojunction bipolar transistor (HBT) having abase region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 ran thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

9. 发明申请

WO2014093217A1 EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION 审中-公开
标题翻译：外来植被极其延伸的地区
公开(公告)号：WO2014093217A1
公开(公告)日：2014-06-19
申请号：PCT/US2013/073857
申请日：2013-12-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ADAM, Thomas, N. , CHENG, Kangguo , DORIS, Bruce, B. , KHAKIFIROOZ, Ali , REZNICEK, Alexander
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/6653 , H01L29/165 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions 340 can be extremely shallow and have an abrupt interface 346 with the channel 307. A dummy gate 310 can establish the position of the abrupt interfaces 346 and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel 307, or to overlap the extension tip.
摘要翻译：公开了一种在保持栅极控制的同时缩小MOSFET结构的方法。 MOSFET的延伸区域通过外延生长形成，并且可以在高温处理完成之后形成。扩展340可以非常浅并且具有与通道307的突然接口346.伪门310可以建立突发接口346的位置，从而限定通道长度。栅电极可以形成为与沟道307完美对准，或者与延伸尖重叠。

10. 发明申请

WO2013173150A1 EPITAXIAL SEMICONDUCTOR RESISTOR WITH SEMICONDUCTOR STRUCTURES ON SAME SUBSTRATE 审中-公开
标题翻译：具有相同基板上的半导体结构的外延半导体电阻
公开(公告)号：WO2013173150A1
公开(公告)日：2013-11-21
申请号：PCT/US2013/040241
申请日：2013-05-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CHENG, Kangguo , KHAKIFIROOZ, Ali , REZNICEK, Alexander , ADAM, Thomas, N.
IPC分类号： H01L21/336 , H01L27/105 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/13 , H01L28/20 , H01L29/0649 , H01L29/36 , H01L29/41783
摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要翻译：提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。外延半导体电阻存在于电阻器件区域中。从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式