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1. 外观设计

USD323495S Facsimile transceiver 失效
公开(公告)号：USD323495S
公开(公告)日：1992-01-28
申请号：US466822
申请日：1990-01-16
申请人： Masayuki Mizuno , Masahiro Hashizume , Shigetoshi Ishikawa
设计人： Masayuki Mizuno , Masahiro Hashizume , Shigetoshi Ishikawa

2. 外观设计

USD358164S Photoconductor unit for forming an image 失效
公开(公告)号：USD358164S
公开(公告)日：1995-05-09
申请号：US13525
申请日：1993-09-27
申请人： Masahiro Hashizume , Hiroshi Ishida , Masayuki Mizuno
设计人： Masahiro Hashizume , Hiroshi Ishida , Masayuki Mizuno

3. 外观设计

USD359754S Developing unit for forming an image 失效
公开(公告)号：USD359754S
公开(公告)日：1995-06-27
申请号：US13546
申请日：1993-09-27
申请人： Masahiro Hashizume , Hiroshi Ishida , Masayuki Mizuno
设计人： Masahiro Hashizume , Hiroshi Ishida , Masayuki Mizuno

4. 发明授权

US08862934B2 Redundant computing system and redundant computing method 有权
标题翻译：冗余计算系统和冗余计算方法
公开(公告)号：US08862934B2
公开(公告)日：2014-10-14
申请号：US13510621
申请日：2010-11-26
申请人： Yoshio Kameda , Masayuki Mizuno
发明人： Yoshio Kameda , Masayuki Mizuno
IPC分类号： G06F11/00 , G06F11/22 , G06F11/07 , G06F11/16
CPC分类号： G06F11/1658 , G06F11/0793 , G06F11/1629 , G06F11/1641 , G06F11/165 , G06F11/1687 , G06F11/2236
摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.
摘要翻译：冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。

5. 发明授权

US08635040B2 Signal measuring device and signal measuring method 失效
标题翻译：信号测量装置及信号测量方法
公开(公告)号：US08635040B2
公开(公告)日：2014-01-21
申请号：US12519837
申请日：2007-12-19
申请人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
发明人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
IPC分类号： G01R13/02
CPC分类号： G01R31/31937 , G01R31/31708 , G01R31/31726
摘要： A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.
摘要翻译：一种信号测量装置，包括测量与测量的驱动时钟信号同步的测量对象的一组或多组测量单元，并将测量结果作为第一数据输出，以及定时识别单元，根据测量开始命令，将与每个周期不同的值作为与具有规定周期和速度低于驱动时钟信号的参考信号同步的第二数据输出; 以及与所述驱动时钟信号同步地收集并依次存储所述第一数据和所述第二数据作为一组的存储单元。

6. 发明授权

US08444316B2 Temperature measuring device and method 失效
标题翻译：温度测量装置及方法
公开(公告)号：US08444316B2
公开(公告)日：2013-05-21
申请号：US12746947
申请日：2008-11-27
申请人： Eisuke Saneyoshi , Koichi Nose , Mikihiro Kajita , Masayuki Mizuno
发明人： Eisuke Saneyoshi , Koichi Nose , Mikihiro Kajita , Masayuki Mizuno
IPC分类号： G01K13/00
CPC分类号： G01K7/01 , G01K2219/00
摘要： Current reading means detects an output current of a current source whose output current varies with a variation in temperature and outputs a value proportional to the output current. The temperature of the current source corresponding to the output value of the current reading means which is proportional to the output current of the current source is measured, and a parameter for converting the output value to temperature information is determined from the output value of the current reading means and the measured value of the temperature of the current source corresponding to the output value. The output value of the current reading means is converted to the temperature information using the determined parameter.
摘要翻译：电流读取装置检测输出电流随温度变化而变化的电流源的输出电流，并输出与输出电流成比例的值。测量与电流读取装置的输出值对应的电流源的温度，其与电流源的输出电流成比例，并且根据电流的输出值确定将输出值转换为温度信息的参数读数手段和对应于输出值的电流源的温度测量值。使用所确定的参数将电流读取装置的输出值转换为温度信息。

7. 发明授权

US08441277B2 Semiconductor testing device, semiconductor device, and testing method 失效
标题翻译：半导体测试装置，半导体器件和测试方法
公开(公告)号：US08441277B2
公开(公告)日：2013-05-14
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

8. 发明授权

US08072253B2 Clock adjusting circuit and semiconductor integrated circuit device 失效
标题翻译：时钟调整电路和半导体集成电路器件
公开(公告)号：US08072253B2
公开(公告)日：2011-12-06
申请号：US12440967
申请日：2007-09-11
申请人： Shunichi Kaeriyama , Masayuki Mizuno
发明人： Shunichi Kaeriyama , Masayuki Mizuno
IPC分类号： H03H11/16
CPC分类号： H03L7/0995 , G06F1/08 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00058 , H03L7/07 , H03L7/0812 , H03L7/0814 , H03L7/0996 , H03L7/0998 , H04L7/0337
摘要： Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.
摘要翻译：公开了一种时钟调节电路，包括：移相器，其接收时钟信号，并且基于控制信号可变地移位时钟信号的上升沿和下降沿的相应定时相位; 以及控制电路，其在每个边缘被输出之前将所述控制信号提供给所述移相器电路; 其中输出时钟信号，其中输入时钟信号的周期，占空比，抖动和偏移/延迟中的至少一个在任意数量的时钟周期上改变。

9. 发明授权

US07908538B2 Failure prediction circuit and method, and semiconductor integrated circuit 有权
标题翻译：故障预测电路及方法，半导体集成电路
公开(公告)号：US07908538B2
公开(公告)日：2011-03-15
申请号：US12438576
申请日：2007-08-09
申请人： Masayuki Mizuno , Toru Nakura , Koichi Nose
发明人： Masayuki Mizuno , Toru Nakura , Koichi Nose
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726 , G01R31/31937
摘要： Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.
摘要翻译：公开了一种半导体集成电路，包括：第一存储电路和第二存储电路，其在时钟线的逻辑电平改变时分别存储对延迟电路的输入的逻辑电平和延迟电路的输出;以及确定电路确定第一存储电路和第二存储电路的结果是否一致。即使构成半导体集成电路的晶体管或布线由于长期变化等而劣化，也可以在异常或异常之前预测由劣化引起的运算电路之一的异常或故障的可能性发生故障

10. 发明授权

US07893742B2 Clock signal dividing circuit 有权
标题翻译：时钟信号分频电路
公开(公告)号：US07893742B2
公开(公告)日：2011-02-22
申请号：US12514115
申请日：2007-10-26
申请人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
发明人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
IPC分类号： H03L7/00
CPC分类号： G06F1/10 , H03K23/507 , H03L7/0814 , H03L7/16
摘要： A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.
摘要翻译：分频比由N / M（M和N是正整数，满足M> N）调节的时钟信号分频电路包括：可变延迟电路，其基于对输入时钟的控制值给出预定的延迟量信号CKI输出输出时钟信号CKO; 以及可变延迟控制电路，当相加结果为N以上时，累积地将通过从输入时钟信号CKI的每个周期从M中减去N而获得的值执行从相加结果中减去N的计算，以获得计算结果K ，并且将对应于输入时钟信号CKI的一个周期的可变延迟电路中的最大延迟量计算为与最大延迟量的K / N的延迟量相对应的控制值，以将控制值赋予该变量延时电路。

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