专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6114744A Semiconductor integration device and fabrication method of the same 失效
标题翻译：半导体集成器件
公开(公告)号：US6114744A
公开(公告)日：2000-09-05
申请号：US38885
申请日：1998-03-12
申请人： Masayuki Kawaguchi , Yasunari Tagami , Hirotsugu Hata , Akira Hatsugai
发明人： Masayuki Kawaguchi , Yasunari Tagami , Hirotsugu Hata , Akira Hatsugai
IPC分类号： H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/42304
摘要： A lead electrode is formed to expose an active base region. A lead electrode for an emitter electrode is formed on the lead electrode in an emitter region, through an insulating film. The insulating film on the lead electrode is then etched to form a contact hole. After that, the emitter contact hole is formed to expose the lead electrode. Also, a silicon nitride film SN is interposed between the lead electrode and insulating film and between the lead electrode and LOCOS oxide film each to decrease resistance of the lead electrodes.
摘要翻译：形成引线电极以暴露活性碱性区域。用于发射极的引线电极通过绝缘膜在发射极区域的引线电极上形成。然后对引线电极上的绝缘膜进行蚀刻以形成接触孔。之后，形成发射极接触孔以露出引线电极。此外，在引线电极和绝缘膜之间以及引线电极和LOCOS氧化物膜之间插入氮化硅膜SN，以降低引线电极的电阻。

2. 发明授权

US6110772A Semiconductor integrated circuit and manufacturing method thereof 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US6110772A
公开(公告)日：2000-08-29
申请号：US16512
申请日：1998-01-30
申请人： Tadayoshi Takada , Tsuyoshi Takahashi , Yasunari Tagami , Hirotsugu Hata , Satoru Kaneko
发明人： Tadayoshi Takada , Tsuyoshi Takahashi , Yasunari Tagami , Hirotsugu Hata , Satoru Kaneko
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/822 , H01L27/06 , H01L21/70
CPC分类号： H01L27/0635 , H01L28/20 , H01L28/40
摘要： A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer. The lower and upper electrodes of the capacitor may be formed using an a-Si layer, similar to the resistance layer.
摘要翻译：一种在电路基板上包括电阻元件的半导体IC。电阻元件包括形成在绝缘层上的电阻层。电阻层使用通过形成a-Si层获得的Si层，用杂质掺杂a-Si层并加热掺杂的a-Si层以扩散杂质而形成，同时基本上保持a-Si层的细度表面。优选地，设置在电阻层下方的SiN层。电容器可以集成在形成电阻元件的同一电路基板上。在这种情况下，依次形成下电极，SiN电介质层和上电极，构成电容器。电容器的SiN介质层形成为从电容器形成区域延伸到另一区域，使得电阻元件的电阻层形成在延伸的SiN电介质层上。可以使用类似于电阻层的a-Si层来形成电容器的下电极和上电极。

3. 发明授权

US6051872A Semiconductor integration device and fabrication method of the same 失效
标题翻译：半导体集成器件及其制造方法相同
公开(公告)号：US6051872A
公开(公告)日：2000-04-18
申请号：US32103
申请日：1998-02-27
申请人： Satoru Kaneko , Masayuki Kawaguchi , Hirotsugu Hata
发明人： Satoru Kaneko , Masayuki Kawaguchi , Hirotsugu Hata
IPC分类号： H01L21/331 , H01L29/417 , H01L29/423 , H01L27/082
CPC分类号： H01L29/66272 , H01L29/41708 , H01L29/42304
摘要： A lead electrode (57) is formed to expose an active base region (61). On the lead electrode (57) is formed a lead electrode (64) for an emitter electrode via an insulation film (56). When a base contact hole (65') for exposing the lead electrode (57) and an emitter contact hole for exposing the lead electrode (64) are formed at the same time, total thickness of the insulation film on the lead electrode (64) is thinner than that of the insulation layer on the lead electrode (57), which results in excessive etching on a part of the surface of the lead electrode to form recess. The lead electrode (64) is led out to a LOCOS film to form the emitter contact hole in a region on the LOCOS film to expose the lead electrode (64). Therefore, the recess having been formed on the lead electrode (64) upon forming the emitter contact hole is made to form on the LOCOS film outside the emitter region. The recess prevents depth of the emitter region from dispersing.
摘要翻译：形成引线电极（57）以暴露活性碱性区域（61）。在引线电极（57）上经由绝缘膜（56）形成用于发射电极的引线电极（64）。当同时形成用于使引线电极（57）露出的基极接触孔（65'）和用于使引线电极（64）露出的发射极接触孔时，引线电极（64）上的绝缘膜的总厚度比引线电极（57）上的绝缘层薄，这导致对引线电极的一部分表面的过度蚀刻以形成凹陷。引线电极（64）被引出到LOCOS膜，以在LOCOS膜上的区域中形成发射极接触孔，以露出引线电极（64）。因此，在形成发射极接触孔的引线电极（64）上形成的凹部被形成在发射极区域外部的LOCOS膜上。该凹口防止发射极区域的深度分散。

4. 发明授权

US07719081B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07719081B2
公开(公告)日：2010-05-18
申请号：US11635813
申请日：2006-12-08
申请人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
发明人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
IPC分类号： H01L21/8228
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.
摘要翻译：在本发明的半导体器件中，在P型单晶硅基板上形成外延层。隔离区形成在外延层中，并被分成多个元件形成区域。在一个元件形成区域中形成NPN晶体管。在P型隔离区域和用作NPN晶体管的基极区域的P型扩散层之间形成N型扩散层。该结构使得基极区域和隔离区域不会短路。因此，能够提高NPN晶体管的击穿电压特性。

5. 发明授权

US07135380B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07135380B2
公开(公告)日：2006-11-14
申请号：US11165083
申请日：2005-06-22
申请人： Satoshi Onai , Hirotsugu Hata
发明人： Satoshi Onai , Hirotsugu Hata
IPC分类号： H01L21/76
CPC分类号： H01L21/763 , H01L21/76224
摘要： In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented. Moreover, in the isolation region, the substantially flat surface makes it possible to form a passive element such as a capacity element.
摘要翻译：在传统的半导体器件制造方法中，存在在隔离区域的形成区域中形成凹部的问题，在隔离区域中不形成平坦面，并且在凹部上方布线层断开。在本发明的半导体器件的制造方法中，当去除用于STI法的氧化硅膜时，部分除去覆盖沟槽内壁的HTO膜，从而在隔离区域形成凹部。此后，将TEOS膜沉积在包括凹部的外延层上并被回蚀刻。因此，绝缘间隔物被埋在凹部中。因此，隔离区域的上表面变为基本平坦的表面。因此，即使在隔离区域中的凹部上方形成布线层，也可以防止其断开。此外，在隔离区域中，基本平坦的表面使得可以形成诸如电容元件的无源元件。

6. 发明授权

US07932580B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932580B2
公开(公告)日：2011-04-26
申请号：US11961516
申请日：2007-12-20
申请人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
发明人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L29/6625 , H01L29/66272 , H01L29/735
摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
摘要翻译：在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。该结构允许减小隔离区域的形成区域。

7. 发明授权

US07560797B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07560797B2
公开(公告)日：2009-07-14
申请号：US11635812
申请日：2006-12-08
申请人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
发明人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
IPC分类号： H01L27/102
CPC分类号： H01L29/7833 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.
摘要翻译：在本发明的半导体器件中，在P型单晶硅衬底上形成两个外延层。一个外延层的杂质浓度高于另一个外延层的杂质浓度。通过隔离区将外延层分成多个元件形成区域。在一个元件形成区域中，形成NPN晶体管。此外，在用作NPN晶体管的基极区域的P型扩散层和P型隔离区域之间，形成N型扩散层。使用这种结构使得在基极区域和隔离区域之间难以发生短路。因此，可以提高NPN晶体管的击穿电压特性。

8. 发明申请

US20080191315A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080191315A1
公开(公告)日：2008-08-14
申请号：US12026593
申请日：2008-02-06
申请人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
发明人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/7322 , H01L21/761 , H01L21/823481 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/66272
摘要： In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.
摘要翻译：在根据本发明的半导体器件中，在P型衬底上形成两个外延层。在衬底和外延层中，形成隔离区以将衬底和外延层分成多个岛。通过将第一和第二P型掩埋层与P型扩散层连接而形成隔离区。通过在第一P型掩埋层和P型扩散层之间设置第二P型掩埋层，第一P型掩埋层的横向扩散宽度减小。通过使用该结构，隔离区域的形成区域的尺寸减小。

9. 发明申请

US20070158754A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070158754A1
公开(公告)日：2007-07-12
申请号：US11635077
申请日：2006-12-07
申请人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
发明人： Mitsuru Soma , Hirotsugu Hata , Minoru Akaishi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7322 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/7833
摘要： In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers are formed by being expanded from a surface of a first epitaxial layer. By use of this structure, lateral expansion widths of the P type buried diffusion layers are reduced. Thus, the device size of an NPN transistor can be reduced.
摘要翻译：在本发明的半导体器件中，在P型单晶硅衬底上形成两个外延层。在外延层中，形成P型掩埋扩散层和P型扩散层，形成隔离区。在这种情况下，P型掩埋扩散层通过从第一外延层的表面扩展而形成。通过这种结构，P型掩埋扩散层的横向膨胀宽度减小。因此，可以减小NPN晶体管的器件尺寸。

10. 发明授权

US08377808B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08377808B2
公开(公告)日：2013-02-19
申请号：US13050345
申请日：2011-03-17
申请人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
发明人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
IPC分类号： H01L21/425
CPC分类号： H01L29/7322 , H01L29/6625 , H01L29/66272 , H01L29/735
摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
摘要翻译：在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。该结构允许减小隔离区域的形成区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式