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1. 发明申请

US20080230899A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080230899A1
公开(公告)日：2008-09-25
申请号：US12053168
申请日：2008-03-21
申请人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
发明人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05085 , H01L2224/05559 , H01L2224/05567 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/3025
摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.
摘要翻译：在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8。形成在焊盘电极3上的金属层9通过覆盖开口区域5〜8而形成有多个凹部10〜13。此外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。通过使用该结构，金属反应区域作为焊盘电极3上的电流路径。因此，焊盘电极3上的电阻值降低。

2. 发明授权

US06875881B2 Preparation of branched tetrasiloxane 有权
标题翻译：支链四硅氧烷的制备
公开(公告)号：US06875881B2
公开(公告)日：2005-04-05
申请号：US10854197
申请日：2004-05-27
申请人： Yasufumi Kubota , Tohru Kubota , Satoshi Onai , Koji Sakuta , Akira Yamamoto
发明人： Yasufumi Kubota , Tohru Kubota , Satoshi Onai , Koji Sakuta , Akira Yamamoto
IPC分类号： C07B61/00 , C07F7/08 , C07F7/18
CPC分类号： C07F7/0874
摘要： A branched tetrasiloxane is prepared by preforming a liquid mixture of a disiloxane compound, an alcohol and an acid catalyst, adding a trialkoxysilane compound to the mixture for reaction, and adding water to the reaction mixture for co-hydrolysis, thereby forming a branched tetrasiloxane. The method is capable of preparing a branched tetrasiloxane, especially methyltris(trimethylsiloxy)silane having a sufficiently high purity to use as cosmetic oil in good yields.
摘要翻译：通过预先制备二硅氧烷化合物，醇和酸催化剂的液体混合物，向混合物中加入三烷氧基硅烷化合物进行反应，并将水加入到用于共水解的反应混合物中，从而形成支链四硅氧烷，制备支链四硅氧烷。该方法能够制备具有足够高纯度的支链四硅氧烷，特别是甲基三（三甲基甲硅烷氧基）硅烷，以高产率用作化妆油。

3. 发明申请

US20080237853A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080237853A1
公开(公告)日：2008-10-02
申请号：US12056751
申请日：2008-03-27
申请人： Yoshimasa AMATATSU , Minoru AKAISHI , Satoshi ONAI , Katsuya OKABE , Yoshiaki SANO , Akira YAMANE
发明人： Yoshimasa AMATATSU , Minoru AKAISHI , Satoshi ONAI , Katsuya OKABE , Yoshiaki SANO , Akira YAMANE
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/05 , H01L23/293 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05014 , H01L2224/05022 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05567 , H01L2224/05572 , H01L2224/05647 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.
摘要翻译：常规的半导体器件具有由于在焊盘电极的表面上形成氧化膜而难以降低焊盘电极之上的电阻值的问题。在本发明的半导体器件中，在焊盘电极上形成氧化防止金属层，并且在氧化防止金属层在形成于旋转涂布树脂膜的开口区域的焊盘电极上方露出。此外，在氧化防止金属层上形成电镀金属层和镀铜层。利用这种结构，焊盘电极上方的电阻值降低，因为焊盘电极的顶表面难以氧化，并且具有比氧化膜小的电阻率的防氧化金属层用作电流路径的一部分。

4. 发明申请

US20060030119A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060030119A1
公开(公告)日：2006-02-09
申请号：US11184262
申请日：2005-07-18
申请人： Satoshi Onai , Toshihiro Okuda
发明人： Satoshi Onai , Toshihiro Okuda
IPC分类号： H01L21/76
CPC分类号： H01L29/66272 , H01L21/763
摘要： There has heretofore been a problem that a junction leak current between a collector and a base is generated by a crystal defect caused in an end portion of a groove adjacent to a base region. In the present invention, an opening is formed in a silicon oxide film and a TEOS film so as to have a distance from an upper end portion of a groove. Thereafter, a base extraction electrode is formed by utilizing the opening. Subsequently, an external base region is formed by solid phase diffusion from the base extraction electrode. In this event, there is secured a distance between the external base region and the upper end portion of the groove. By use of the manufacturing method described above, it is possible to suppress generation of a junction leak current between a collector and a base.
摘要翻译：迄今为止，存在在与基底区域相邻的凹槽的端部处产生的晶体缺陷产生集电体和基底之间的结漏电流的问题。在本发明中，在氧化硅膜和TEOS膜中形成有与槽的上端部隔开的距离的开口部。此后，通过利用开口形成基极引出电极。随后，通过从基极引出电极的固相扩散形成外部基极区域。在这种情况下，固定了外部基部区域和槽的上端部分之间的距离。通过使用上述制造方法，可以抑制集电体与基体之间的结漏电流的产生。

5. 发明授权

US08013442B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08013442B2
公开(公告)日：2011-09-06
申请号：US12053168
申请日：2008-03-21
申请人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
发明人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05085 , H01L2224/05559 , H01L2224/05567 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/3025
摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.
摘要翻译：在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8.形成在焊盘电极3上的金属层9具有形成的多个凹部10至13 另外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。通过使用这种结构，金属反应区域用作焊盘电极3上的电流路径。因此，焊盘电极3上的电阻值减小。

6. 发明授权

US07135380B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07135380B2
公开(公告)日：2006-11-14
申请号：US11165083
申请日：2005-06-22
申请人： Satoshi Onai , Hirotsugu Hata
发明人： Satoshi Onai , Hirotsugu Hata
IPC分类号： H01L21/76
CPC分类号： H01L21/763 , H01L21/76224
摘要： In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented. Moreover, in the isolation region, the substantially flat surface makes it possible to form a passive element such as a capacity element.
摘要翻译：在传统的半导体器件制造方法中，存在在隔离区域的形成区域中形成凹部的问题，在隔离区域中不形成平坦面，并且在凹部上方布线层断开。在本发明的半导体器件的制造方法中，当去除用于STI法的氧化硅膜时，部分除去覆盖沟槽内壁的HTO膜，从而在隔离区域形成凹部。此后，将TEOS膜沉积在包括凹部的外延层上并被回蚀刻。因此，绝缘间隔物被埋在凹部中。因此，隔离区域的上表面变为基本平坦的表面。因此，即使在隔离区域中的凹部上方形成布线层，也可以防止其断开。此外，在隔离区域中，基本平坦的表面使得可以形成诸如电容元件的无源元件。

7. 发明申请

US20060030111A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060030111A1
公开(公告)日：2006-02-09
申请号：US11184213
申请日：2005-07-18
申请人： Satoshi Onai , Shinobu Teranaka
发明人： Satoshi Onai , Shinobu Teranaka
IPC分类号： H01L21/336
CPC分类号： H01L29/66272 , H01L29/7322
摘要： There has heretofore been a problem that desired withstanding characteristics cannot be obtained since a buried diffusion layer climbs up more than necessary in other heat treatment steps. In the present invention, after an N-type buried diffusion layer is formed, dry etching is performed in order to round off corner portions of a groove used for inter-element isolation and the like. Moreover, the groove is filled up with an NSG film formed by use of a CVD method, for example. Furthermore, a trench forming an isolation region is filled up with a HTO film and a polycrystalline silicon film, which are formed by use of the CVD method, for example. By use of the manufacturing method described above, it is possible to realize a semiconductor device capable of obtaining desired withstanding characteristics by preventing the N-type buried diffusion layer from climbing up more than necessary.
摘要翻译：迄今为止，由于掩埋扩散层在其它热处理步骤中爬升超过必要，所以存在无法获得期望的耐受特性的问题。在本发明中，在形成N型掩埋扩散层之后，进行干蚀刻以使用于元件间隔离等的凹槽的角部圆整。此外，例如，通过使用CVD法形成的NSG膜填充凹槽。此外，形成隔离区的沟槽填充有例如通过使用CVD法形成的HTO膜和多晶硅膜。通过使用上述制造方法，可以实现能够通过防止N型埋入扩散层上升超过所需的能够获得期望的耐受特性的半导体器件。

8. 发明申请

US20100164105A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100164105A1
公开(公告)日：2010-07-01
申请号：US12646173
申请日：2009-12-23
申请人： Satoshi ONAI , Minoru Akaishi , Hiroshi Ishizeki , Yoshiaki Sano
发明人： Satoshi ONAI , Minoru Akaishi , Hiroshi Ishizeki , Yoshiaki Sano
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05556 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85 , H01L2224/85205 , H01L2924/00011 , H01L2924/00015 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/05042 , H01L2924/10253 , H01L2924/13091 , H01L2924/00014 , H01L2924/00 , H01L2924/01006
摘要： An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.
摘要翻译：在通过在铜布线上的部分上引线接合铜线形成的半导体器件中，目的是防止铜线下的绝缘膜中的布线分离或裂纹等的故障。根据本发明的半导体器件包括形成在半导体衬底上的铜布线，形成为覆盖铜布线的顶表面和侧表面的镀层和在镀层上引线接合的铜线铜线上方。

9. 发明申请

US20080258301A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20080258301A1
公开(公告)日：2008-10-23
申请号：US12081487
申请日：2008-04-16
申请人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
发明人： Yoshimasa Amatatsu , Minoru Akaishi , Satoshi Onai , Katsuya Okabe , Yoshiaki Sano , Akira Yamane
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76816 , H01L21/32051 , H01L21/76838 , H01L21/76843 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53223 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/11462 , H01L2224/1148 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014 , H01L2224/05552
摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.
摘要翻译：常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

10. 发明申请

US20050287765A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050287765A1
公开(公告)日：2005-12-29
申请号：US11165083
申请日：2005-06-22
申请人： Satoshi Onai , Hirotsugu Hata
发明人： Satoshi Onai , Hirotsugu Hata
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/76224
摘要： In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented. Moreover, in the isolation region, the substantially flat surface makes it possible to form a passive element such as a capacity element.
摘要翻译：在传统的半导体器件制造方法中，存在在隔离区域的形成区域中形成凹部的问题，在隔离区域中不形成平坦面，并且在凹部上方布线层断开。在本发明的半导体器件的制造方法中，当除去用于STI法的氧化硅膜时，部分除去覆盖沟槽内壁的HTO膜，从而在隔离区域形成凹部。此后，将TEOS膜沉积在包括凹部的外延层上并被回蚀刻。因此，绝缘间隔物被埋在凹部中。因此，隔离区域的上表面变为基本平坦的表面。因此，即使在隔离区域中的凹部上方形成布线层，也可以防止其断开。此外，在隔离区域中，基本平坦的表面使得可以形成诸如电容元件的无源元件。

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