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1. 发明授权

US6150800A Power circuit including inrush current limiter, and integrated circuit including the power circuit 有权
标题翻译：包括浪涌电流限制器的电源电路和包括电源电路的集成电路
公开(公告)号：US6150800A
公开(公告)日：2000-11-21
申请号：US395971
申请日：1999-09-15
申请人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
发明人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
IPC分类号： G05F1/56 , G05F1/573 , G05F1/575 , H02H9/02 , G05F1/40
CPC分类号： G05F1/573 , G05F1/575 , Y10S323/908
摘要： A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.
摘要翻译：描述了一种电源电路，其包括用于在电源电路的初始操作期间防止产生浪涌电流的装置，而不增加电源电路的尺寸。电源电路包括用于从电源向输出端子提供电流的输出晶体管，以及差分放大器，用于根据预设的方式控制由输出晶体管提供的电流，以调节输出端子处的电压参考电压。在差分放大器的输出级的电流路径上提供限制晶体管作为源极跟随器。使用限制晶体管的源极电位来控制输出晶体管的栅极电位。在电源电路开始工作之前，操作控制器对电容器充电以控制限流晶体管的栅极电位，使得在电源电路的初始操作期间，通过使用电流源来放电电容器。因此，在电源电路的初始动作期间，限制晶体管的栅极电位逐渐降低，同时输出晶体管的栅极 - 源极电压逐渐增大。结果，可以抑制浪涌电流的产生。

2. 发明授权

US06429633B1 Switching regulator and LSI system 失效
标题翻译：开关稳压器和LSI系统
公开(公告)号：US06429633B1
公开(公告)日：2002-08-06
申请号：US09530267
申请日：2000-04-28
申请人： Jun Kajiwara , Katsuji Satomi , Shiro Sakiyama , Masayoshi Kinoshita , Katsuhiro Ootani
发明人： Jun Kajiwara , Katsuji Satomi , Shiro Sakiyama , Masayoshi Kinoshita , Katsuhiro Ootani
IPC分类号： G05F140
CPC分类号： H03K17/164
摘要： In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.
摘要翻译：在开关稳压器中，开关噪声降低，保持高的转换效率。开关调节器包括具有不同导通电阻的多个输出开关晶体管21至23，它们在接通操作中工作时导通电阻的下降顺序，并且在关断操作中以导通电阻的升序操作。以这种方式，可以在开关操作中抑制突然的电流变化，从而减少从寄生电感器102得到的di / dt噪声。

3. 发明授权

US06307360B1 Switching regulator DC/DC converter, and LSI system provided with switching regulator 有权
标题翻译：开关稳压器DC / DC转换器和配有开关稳压器的LSI系统
公开(公告)号：US06307360B1
公开(公告)日：2001-10-23
申请号：US09673851
申请日：2000-10-23
申请人： Jun Kajiwara , Shiro Sakiyama , Masayoshi Kinoshita , Katsuji Satomi , Katsuhiro Ootani
发明人： Jun Kajiwara , Shiro Sakiyama , Masayoshi Kinoshita , Katsuji Satomi , Katsuhiro Ootani
IPC分类号： G05F1563
CPC分类号： H02M1/36 , H02M1/32 , H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.
摘要翻译：同步整流模式的开关调节器包括串联布置在电源Vdd和接地Vss之间的第一和第二开关SW1，SW2，开关控制单元1，其控制开关SW1，SW2的开关操作，以及平滑电路4，其平滑输出节点电位Vnd。当信号Sc1表示输出节点电位Vnd低于第一基准电位Vr1时，第一参考电位Vr1是第一开关SW1处于导通状态时检测涌流的发生的基准，控制电路10关闭第一开关 SW1。因此，通过利用由于第一开关SW1的导通电阻引起的电压降来进行浪涌电流的检测，从而不需要提供用于检测浪涌电流的电阻元件。

4. 发明授权

US06490715B1 Cell library database and design aiding system 有权
标题翻译：细胞库数据库和设计辅助系统
公开(公告)号：US06490715B1
公开(公告)日：2002-12-03
申请号：US09550352
申请日：2000-04-14
申请人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
发明人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.
摘要翻译：单元库数据库包括作为形成逻辑装置的基本电路的标准单元的功能信息，标准单元中的每一个包括作为逻辑端的电源端子中的至少一个，包含逻辑信息或延迟信息的标准单元的功能信息所述电源端子相对于输出端子，或作为形成逻辑装置的功能电路的宏电池的功能信息，所述宏电池单元包括作为逻辑端子的电源端子中的至少一个，所述宏单元的功能信息包含所述电源端子相对于输出端子的逻辑信息或延迟信息。设计辅助系统使用单元库数据库执行逻辑仿真等。

5. 发明授权

US06686782B2 Power supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US06686782B2
公开(公告)日：2004-02-03
申请号：US10053552
申请日：2002-01-24
申请人： Masayoshi Kinoshita , Jun Kajiwara , Shiro Sakiyama
发明人： Masayoshi Kinoshita , Jun Kajiwara , Shiro Sakiyama
IPC分类号： H03K1722
CPC分类号： G01R19/16538 , H03K17/223
摘要： A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground. Until the output voltage from the comparison circuit is higher than the threshold voltage of the PMOS transistor, the PMOS transistor remains OFF, thereby canceling the input of the output voltage signal from the voltage division circuit to the comparison circuit. Thus, without using external components, the signal is prevented from being erroneously output due to the output voltage from the voltage division circuit rising over, without crossing, the reference voltage from the reference voltage circuit during a sharp rise of the power supply voltage.
摘要翻译：电源电压检测电路包括用于线性分割电源电压的分压电路，用于提供参考电压的参考电压电路和用于比较来自分压电路的输出电压和参考电压的参考电压的比较电路电压电路。电源电压检测电路在检测到电源电压等于或高于参考电压时输出信号。在分压电路和比较电路之间设置PMOS晶体管。 PMOS晶体管包括连接到分压电路的输出端的源极端子，连接到比较电路的输入端子的漏极端子和连接到地的栅极端子。在比较电路的输出电压高于PMOS晶体管的阈值电压之前，PMOS晶体管保持截止状态，从而消除从分压电路到比较电路的输出电压信号的输入。因此，在不使用外部部件的情况下，由于来自分压电路的输出电压在电源电压的急剧上升期间不与基准电压电路交叉而不会交叉，所以不会错误地输出信号。

6. 发明授权

US06531856B2 Power source system for reducing power consumption in an intermittent mode of operation 失效
标题翻译：电源系统，用于在间歇运行模式下降低功耗
公开(公告)号：US06531856B2
公开(公告)日：2003-03-11
申请号：US09920670
申请日：2001-08-03
申请人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： G05F140
CPC分类号： H02M1/15 , H02J7/345
摘要： During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.
摘要翻译：在间歇操作模式期间，开关通常被打开，并且具有大电容的电容器与电路隔离。在这种情况下，电源电压被间歇地供给到被驱动装置。由于在间歇操作模式期间电容器的充电/放电电流被限制为具有小电容的电容器的充电/放电电流，所以可以降低功耗。此外，由于在从电源电压转换电路到被驱动装置的电流路径中不存在开关，因此从电源电压转换电路向被驱动装置提供的电压不会由于开关而下降。另一方面，在向被驱动装置连续提供电源电压的连续运转模式中，开关常闭，电容器电容器与电源系统连接。然后降低供电电源中的噪声电平。

7. 发明授权

US06914259B2 Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module 失效
标题翻译：多芯片模块，半导体芯片和芯片间连接测试方法
公开(公告)号：US06914259B2
公开(公告)日：2005-07-05
申请号：US10262669
申请日：2002-10-02
申请人： Shiro Sakiyama , Masayoshi Kinoshita , Jun Kajiwara
发明人： Shiro Sakiyama , Masayoshi Kinoshita , Jun Kajiwara
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/822 , H01L23/52 , H01L25/18 , H01L27/04 , H01L23/58
CPC分类号： G11C29/022 , G01R31/2853 , G01R31/318505 , G01R31/318513 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.
摘要翻译：通过经由多个导电连接构件连接设置在例如两个半导体芯片上的多个连接焊盘来实现多芯片模块。为了进行用于确定两个半导体芯片之间的连接质量的测试，多芯片模块还设置有多个开关元件，使得多个连接构件可以经由连接以串联方式导电半导体芯片的焊盘。在连接测试期间，所有的开关元件都被接通，并且使用两个探测器来测量包括以串行方式传导的多个连接构件的线的两端之间的阻抗。

8. 发明授权

US06833626B2 Multichip module structure 失效
标题翻译：多芯片模块结构
公开(公告)号：US06833626B2
公开(公告)日：2004-12-21
申请号：US10189549
申请日：2002-07-08
申请人： Jun Kajiwara , Masayoshi Kinoshita , Shiro Sakiyama
发明人： Jun Kajiwara , Masayoshi Kinoshita , Shiro Sakiyama
IPC分类号： H01L2940
CPC分类号： H01L25/16 , G01R31/2853 , G01R31/318513 , H01L27/10897 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/01019 , H01L2924/3011 , H01L2224/05599
摘要： A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.
摘要翻译：大芯片包括从第一干线导线分支并延伸到相应导线的第一组支线，以便连接到相应的接合焊盘。第一组的每条分支线包括连接控制元件和电阻器。小芯片包括从第二干线分支的第二组支线，并延伸到相应的导线，以便连接到相应的接合焊盘。第二组的每条分支线包括连接控制元件和电阻器。通过在对第一和第二测试焊盘施加电压时测量电流值来确定接合焊盘之间是否正确地进行连接。

9. 发明授权

US06646342B2 Semiconductor chip and multi-chip module 有权
公开(公告)号：US06646342B2
公开(公告)日：2003-11-11
申请号：US10097140
申请日：2002-03-14
申请人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： H01L2334
CPC分类号： H01L23/50 , H01L23/5382 , H01L23/5383 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

10. 发明授权

US06462427B2 Semiconductor chip, set of semiconductor chips and multichip module 有权
标题翻译：半导体芯片，半导体芯片和多芯片模块
公开(公告)号：US06462427B2
公开(公告)日：2002-10-08
申请号：US10024721
申请日：2001-12-21
申请人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： H01L2940
CPC分类号： H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/19105 , H01L2924/3011 , H01L2224/05624 , H01L2924/00014
摘要： Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.
摘要翻译：每个裸芯片IP包括具有相同尺寸和形状的相同材料的焊盘电极，并且在其几乎整个表面上以相同的间距排列成阵列。硅布线基板包括以与裸芯片IP的焊盘电极之间相同的间距排列成几乎整个表面的阵列电极。裸芯片IP安装在硅布线基板上，从而形成多芯片模块。

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