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1. 发明申请

US20090138840A1 CELL, STANDARD CELL, STANDARD CELL LIBRARY, A PLACEMENT METHOD USING STANDARD CELL, AND A SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：细胞，标准细胞，标准细胞库，使用标准细胞的放置方法和半导体集成电路
公开(公告)号：US20090138840A1
公开(公告)日：2009-05-28
申请号：US12359615
申请日：2009-01-26
申请人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
发明人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L27/11807
摘要： A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
摘要翻译：根据本发明的单元包括能够传输输入信号或输出信号并在设计半导体集成电路中作为最小单位的多个端子，其中多个端子位于沿Y方向排列的布线栅格上其是与用于自动布置和布线的电池的电源布线垂直的方向，并且具有在与电源布线并联的方向的X方向上延伸的形状，更具体地说，例如，终端的长边尺寸等于“X方向上的路由网格间隔+布线宽度”，根据该结构，小区面积减小，有利于芯片面积的减少。

2. 发明申请

US20060136848A1 Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit 有权
公开(公告)号：US20060136848A1
公开(公告)日：2006-06-22
申请号：US11305191
申请日：2005-12-19
申请人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
发明人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , H01L27/11807
摘要： A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

3. 发明授权

US06895564B2 Method for designing LSI system 失效
标题翻译： LSI系统设计方法
公开(公告)号：US06895564B2
公开(公告)日：2005-05-17
申请号：US10078469
申请日：2002-02-21
申请人： Mikawa Takahashi , Hiroshi Mizuno , Toshiyuki Moriwaki , Hiroki Shinde
发明人： Mikawa Takahashi , Hiroshi Mizuno , Toshiyuki Moriwaki , Hiroki Shinde
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A design technique considering a peak current is provided for high-level design of systems including LSIs. A hardware model representing the trade-off relationship between a leak current and performance is prepared in advance for functional units constituting the system. In the hardware model, the relationship between performance tpd and a source-drain leak current Pleak is described with a threshold voltage Vth as a parameter, for example. By referring to the trade-off relationship, design conditions for the functional units are determined under evaluation of the performance and power consumption of the entire system.
摘要翻译：考虑到峰值电流的设计技术是为包括LSI的系统的高级设计提供的。对于构成系统的功能单元，预先准备表示泄漏电流与性能之间的权衡关系的硬件模型。在硬件模型中，例如以阈值电压Vth为参数来描述性能tpd与源漏泄漏电流Pleak之间的关系。通过参考权衡关系，对整个系统的性能和功耗进行评估，确定功能单元的设计条件。

4. 发明授权

US06301692B1 Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
标题翻译：用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法
公开(公告)号：US06301692B1
公开(公告)日：2001-10-09
申请号：US09153063
申请日：1998-09-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

5. 发明申请

US20090045568A1 Sheet material accumulating apparatus 有权
标题翻译：片料积存装置
公开(公告)号：US20090045568A1
公开(公告)日：2009-02-19
申请号：US11921939
申请日：2006-05-23
申请人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
发明人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
IPC分类号： B65H31/06
CPC分类号： B65H31/06 , B65H15/00 , B65H29/66 , B65H2301/33212 , B65H2301/3423 , B65H2301/42146 , B65H2402/10 , B65H2402/351 , B65H2404/2611 , B65H2511/15 , B65H2701/1912
摘要： A sheet material accumulating apparatus for accumulating a sheet material W into an accumulated bundle P by arranging it in a mutually overlapping state is configured to be able to suppress an enlargement, a higher tallness, more complication, etc. of the apparatus and attain a curtailment of various costs, including a manufacture cost.The apparatus has a primary conveyer 2, a second conveyer 3, and an accumulation unit 4, the accumulation unit 4 has a posture conversion unit 35 for converting the sheet material W in a flatted posture into that in a standing posture, a descend conveyer unit 36 for conveying the sheet material W downward while keeping the standing posture, and a table top 7 for accumulating the received sheet material W sequentially while supporting it in a standup posture; the primary conveyer 2 has a flat conveyance plane 6 at a substantially same height as the table top 7; and the secondary conveyer 3 twists the sheet material W along a conveyance direction so that top and bottom thereof may be inverted while it is conveyed in a rise inclined direction.
摘要翻译：通过将片状材料W以相互重叠的状态配置而将片材W堆积成堆积束P的片材积蓄装置被构造成能够抑制装置的放大，更高的高度，更加复杂等，并且实现削减各种成本，包括制造成本。该装置具有主输送机2，第二输送机3和累积单元4，积存单元4具有姿势转换单元35，用于将处于平坦姿势的片材W转换成立式姿势转换单元35，下降输送单元 36，用于在保持站立姿势的同时向下传送片材W;以及台面7，用于在支撑姿势的同时顺序地收纳接收的片材W; 主输送机2具有与桌面7基本相同的高度的平坦输送平面6; 二次输送机3沿着输送方向扭转片材W，使得其在顶部和底部沿上升倾斜方向输送时可以倒置。

6. 发明授权

US06967866B2 Semiconductor memory and semiconductor integrated circuit 有权
标题翻译：半导体存储器和半导体集成电路
公开(公告)号：US06967866B2
公开(公告)日：2005-11-22
申请号：US10800711
申请日：2004-03-16
申请人： Akio Hirata , Toshiyuki Moriwaki , Tetsurou Toubou , Nana Okamoto , Mitsuaki Hayashi
发明人： Akio Hirata , Toshiyuki Moriwaki , Tetsurou Toubou , Nana Okamoto , Mitsuaki Hayashi
IPC分类号： G11C17/08 , G11C11/34 , G11C17/00 , G11C17/12 , H01L21/82 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/112
CPC分类号： G11C17/12
摘要： A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.
摘要翻译：包括伪栅极的虚设MOSFET将沿着位线延伸的方向排列的相邻存储单元中包括的nMOSFET分离。这种配置减小了从STI施加到nMOSFET的沟道区域的应力。因此，抑制了nMOSFET的驱动电流的降低。

7. 发明授权

US06922443B1 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US06922443B1
公开(公告)日：2005-07-26
申请号：US09712247
申请日：2000-11-15
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H03K19/096 , H03K17/04 , H03K19/0175 , H04L25/02 , H04L25/03 , H04B3/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
摘要翻译：与重复分别表示准备期间和发送期间的H，L电平的时钟信号同步地发送信号。发送电路包括发送电容器，用于在准备期间根据发送电容器中的输入数字信号设定电压的输入开关和用于在发送期间产生信号线中的小电压变化的发送开关，根据发送电容器的电压进行变化。接收电路包括具有CMOS配置的反相器，插入在反相器的输入端子和输出端子之间的接收电容器，用于使逆变器的输入端子和输出端子短路的均衡开关，以便设置电压的信号线在预备期间达到预定电压，以及锁存器，用于通过在每个传输周期内执行对逆变器的输出端子的电压的逻辑放大来提供输出数字信号，并且用于保持每个准备周期的输出。

8. 发明授权

US5983008A Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
标题翻译：用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法
公开(公告)号：US5983008A
公开(公告)日：1999-11-09
申请号：US153333
申请日：1998-09-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

9. 发明授权

US5923569A Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof 失效
标题翻译：通过用于验证其定时的相同方法和方法获得的半导体集成电路半导体集成电路布局的设计方法
公开(公告)号：US5923569A
公开(公告)日：1999-07-13
申请号：US732808
申请日：1996-10-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

10. 发明授权

US07737472B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07737472B2
公开(公告)日：2010-06-15
申请号：US12061947
申请日：2008-04-03
申请人： Hideaki Kondo , Toshiyuki Moriwaki , Masaki Tamaru , Takashi Andoh
发明人： Hideaki Kondo , Toshiyuki Moriwaki , Masaki Tamaru , Takashi Andoh
IPC分类号： H01L29/72
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
摘要翻译：提供能够抑制由于良好邻近效应引起的晶体管特性变化的半导体集成电路器件。标准单元行排列成垂直方向，每个标准单元行包括沿水平方向布置的标准单元。在标准单元行中，N阱和P区域在垂直方向上的位置每隔一行被切换。相邻的标准单元行共享P区或N阱。位于标准单元行的端部到N阱的端部的PMOS晶体管的距离大于或等于标准单元行共享的N阱的宽度。

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