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1. 发明授权

US07881376B2 Motion compensation apparatus 有权
标题翻译：运动补偿装置
公开(公告)号：US07881376B2
公开(公告)日：2011-02-01
申请号：US11126291
申请日：2005-05-11
申请人： Masayasu Iguchi , Hiroaki Toida , Toshiyasu Sugio
发明人： Masayasu Iguchi , Hiroaki Toida , Toshiyasu Sugio
IPC分类号： H04N7/12
CPC分类号： H04N19/577 , H04N19/523 , H04N19/533 , H04N19/57 , H04N19/573
摘要： A motion compensation apparatus reduces the number of pixels for reading out pixel data from the multi-frame memory, and realizes the reduction of transmission and motion compensation in sub-pixel precision pixel generation, for efficient motion compensation pixel generation. The motion compensation apparatus includes a frame memory transmission control unit which, with regard to a plurality of motion compensation blocks, transmits reference pixels required in motion compensation collectively or on a per motion compensation block basis, from a multi-frame memory which stores a reference picture used in inter-picture motion compensation prediction, to a local reference memory.
摘要翻译：运动补偿装置减少用于从多帧存储器读出像素数据的像素数量，并且实现子像素精度像素生成中的传输和运动补偿的减少，用于有效的运动补偿像素生成。运动补偿装置包括：帧存储器发送控制单元，对于多个运动补偿块，从存储参考的多帧存储器中，一体地或者以运动补偿块为基础，发送运动补偿所需的参考像素用于画面间运动补偿预测的图像，到本地参考存储器。

2. 发明申请

US20050254581A1 Motion compensation apparatus 有权
标题翻译：运动补偿装置
公开(公告)号：US20050254581A1
公开(公告)日：2005-11-17
申请号：US11126291
申请日：2005-05-11
申请人： Masayasu Iguchi , Hiroaki Toida , Toshiyasu Sugio
发明人： Masayasu Iguchi , Hiroaki Toida , Toshiyasu Sugio
IPC分类号： H04N19/50 , H04N7/12 , H04N19/423 , H04N19/503 , H04N19/51 , H04N19/523 , H04N19/573
CPC分类号： H04N19/577 , H04N19/523 , H04N19/533 , H04N19/57 , H04N19/573
摘要： A motion compensation apparatus is provided, which can reduce the number of pixels for reading out pixel data from the multi-frame memory, and can realize the reduction of transmission and motion compensation in sub-pixel precision pixel generation, for efficient motion compensation pixel generation. The motion compensation apparatus includes a frame memory transmission control unit which, with regard to a plurality of motion compensation blocks, transmits reference pixels required in motion compensation collectively or on a per motion compensation block basis, from a multi-frame memory which stores a reference picture used in inter-picture motion compensation prediction, to a local reference memory.
摘要翻译：提供一种运动补偿装置，其可以减少用于从多帧存储器读出像素数据的像素数量，并且可以实现子像素精度像素生成中的传输和运动补偿的减少，用于有效的运动补偿像素生成。运动补偿装置包括：帧存储器发送控制单元，对于多个运动补偿块，从存储参考的多帧存储器中，一体地或者以运动补偿块为基础，发送运动补偿所需的参考像素用于画面间运动补偿预测的图像，到本地参考存储器。

3. 发明申请

US20070258702A1 Encoding or Decoding Device and Recording/Reproduction Terminal 审中-公开
标题翻译：编码或解码设备和录制/再现终端
公开(公告)号：US20070258702A1
公开(公告)日：2007-11-08
申请号：US10565131
申请日：2005-06-20
申请人： Toshiyasu Sugio , Hiroaki Toida , Takahiro Nishi , Tadamasa Toma , Hisao Sasai
发明人： Toshiyasu Sugio , Hiroaki Toida , Takahiro Nishi , Tadamasa Toma , Hisao Sasai
IPC分类号： H04N7/26
CPC分类号： H04N9/7921 , G06F1/1626 , G06F1/1656 , G06F1/1686 , H04N5/232 , H04N5/772 , H04N5/781 , H04N5/782 , H04N5/907 , H04N7/012 , H04N9/8042 , H04N9/8063 , H04N9/8205 , H04N19/103 , H04N19/132 , H04N19/156 , H04N19/172 , H04N19/182 , H04N19/40
摘要： An object of the present invention is to provide a recording/reproduction terminal having a general-purpose slot and a detachable encoding or decoding device. A recording/reproduction device includes: a recording/reproduction terminal 103 which records and reproduces signals representing audio or video; and a removable coding device 100 which is detachably connected to the recording/reproduction terminal 103, and the recording/reproduction terminal 103 has a terminal information storage unit 105 which stores terminal information which is information regarding the recording/reproduction terminal 103, and a removable coding device 100 has: a terminal information obtainment unit 101 which obtains the terminal information from the recording/reproduction terminal 103 when the removable coding device 100 is connected to the recording/reproduction terminal 103; and a signal conversion unit 102 which encodes or decodes the signals representing audio or video based on the obtained terminal information.
摘要翻译：本发明的目的是提供一种具有通用时隙和可拆卸编码或解码装置的记录/再现终端。记录/再现装置包括：记录和再现表示音频或视频的信号的记录/再现终端103; 以及可拆卸地连接到记录/再现终端103的可移除编码装置100，并且记录/再现终端103具有终端信息存储单元105，其存储关于记录/再现终端103的信息的终端信息，以及可移除编码装置100具有：终端信息获取单元101，当可移除编码装置100连接到记录/再现终端103时，其从记录/再现终端103获得终端信息; 以及信号转换单元102，其基于获得的终端信息对表示音频或视频的信号进行编码或解码。

4. 发明授权

US07724830B2 Decoding-processing apparatus and method 有权
标题翻译：解码处理装置和方法
公开(公告)号：US07724830B2
公开(公告)日：2010-05-25
申请号：US11665063
申请日：2005-11-02
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

5. 发明申请

US20090225865A1 Decoding-Processing Apparatus And Method 有权
标题翻译：解码处理装置及方法
公开(公告)号：US20090225865A1
公开(公告)日：2009-09-10
申请号：US11665063
申请日：2005-11-02
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/26 , H04L27/00
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus (1) comprising: a context-calculating unit (2) operable to calculate the probability of symbols contained in incoming bitstreams; a parameter-generating unit (3) operable to generate parameters for use in the context-calculating unit (2); an arithmetic decoding-calculating unit (4) operable to decode the incoming bitstreams in accordance with the probability, thereby providing decoded data; a stream-converting unit (5) operable to convert the decoded data into intermediate bitstreams; a storage unit (6) operable to store the intermediate bitstreams; a synchronization-detecting unit (7) operable to detect calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing; and a multivalued calculating unit (8) operable to permit the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种解码处理装置（1），包括：上下文计算单元（2），用于计算输入比特流中包含的符号的概率; 参数产生单元（3），用于产生在所述上下文计算单元（2）中使用的参数; 算术解码计算单元，用于根据概率解码输入比特流，从而提供解码数据; 流转换单元（5），用于将解码数据转换成中间比特流; 存储单元（6），用于存储中间比特流; 同步检测单元，用于从存储单元（6）馈送的中间比特流检测计算开始定时，从而提供检测到的计算开始时刻; 以及多值计算单元（8），其可操作以允许从所述同步检测单元（7）与所检测到的计算开始定时同步地将从所述存储单元（6）馈送的中间比特流多值化。

6. 发明授权

US08179972B2 Image encoding device, image decoding device, and integrated circuit used therein 有权
标题翻译：图像编码装置，图像解码装置及其中使用的集成电路
公开(公告)号：US08179972B2
公开(公告)日：2012-05-15
申请号：US11628733
申请日：2005-06-07
申请人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
发明人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
IPC分类号： H04N7/12
CPC分类号： H04N19/42 , H04N19/122 , H04N19/60
摘要： An image decoding device and an encoding device include an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing.
摘要翻译：图像解码装置和编码装置包括用于进行运算处理的算术单元，运算单元存储运算结果的算术数据存储单元，选择是否读入要输入的像素数据的输入选择单元从压缩图像数据或从存储在算术数据存储单元中的像素数据获得的运算单元，以及将读取的像素数据输入到运算单元，以及运算控制单元，用于根据所使用的变换模式和算术运算数，算术单元，读取由输入选择单元输入到运算单元的像素数据的目的地以及由算术单元进行算术处理的像素数据的组合和乘法系数，算术处理。

7. 发明授权

US08406308B2 Encoding apparatus for encoding binary signals generated from binarized multivalued syntax elements and method for performing the same 有权
标题翻译：用于编码由二值化多值语法元素生成的二进制信号的编码装置及其执行方法
公开(公告)号：US08406308B2
公开(公告)日：2013-03-26
申请号：US12761493
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.
摘要翻译：使用算术编码对二进制信号进行编码的编码装置。编码装置包括二值化单元，二值化多值语法元素以便生成二进制信号。生成的二进制信号存储在中间缓冲器上。此外，编码装置包括对存储在中间缓冲器上的二进制信号执行算术编码的算术编码单元。另外，生成的二进制信号是多值语法元素的值的二进制表示。

8. 发明申请

US20080049832A1 Image Encoding Device, Image Decoding Device, and Integrated Circuit Used Therein 有权
标题翻译：图像编码装置，图像解码装置及其中使用的集成电路
公开(公告)号：US20080049832A1
公开(公告)日：2008-02-28
申请号：US11628733
申请日：2005-06-07
申请人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
发明人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
IPC分类号： H04B1/66
CPC分类号： H04N19/42 , H04N19/122 , H04N19/60
摘要： An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transform mode for each unit executable in one arithmetic operation in the arithmetic unit in association with the number of arithmetic operations.
摘要翻译：根据本发明的图像解码装置和图像编码装置包括：运算单元，用于进行运算处理;算术数据存储单元，用于存储运算单元的算术结果;输入选择单元，用于选择是否读取像素数据，从压缩图像数据或从存储在算术数据存储单元中的像素数据输入到运算单元，并将读取的像素数据输入到运算单元，以及运算控制单元，用于基于所使用的变换模式和算术单元中的算术运算的数量，由输入选择单元输入到运算单元的像素数据的目的地以及由运算单元计算的运算处理对象的像素数据的组合算术单元和乘法器系数，运算控制单元先前定义算术在算术单元中的一个算术运算中，每个单元的每个变换模式的过程与算术运算的数量相关联。

9. 发明授权

US08081683B2 Decoding-processing apparatus for decoding bitstreams encoded in accordance with an arithmetic-encoding system in image compression and method for performing the same 有权
标题翻译：用于对图像压缩中的算术编码系统进行编码的比特流进行解码的解码处理装置及其执行方法
公开(公告)号：US08081683B2
公开(公告)日：2011-12-20
申请号：US12761507
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

10. 发明申请

US20100232516A1 DECODING-PROCESSING APPARATUS AND METHOD 有权
标题翻译：解码处理设备和方法
公开(公告)号：US20100232516A1
公开(公告)日：2010-09-16
申请号：US12761507
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/26
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

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