会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Method for manufacturing a semiconductor device
    • 半导体器件的制造方法
    • US07892973B2
    • 2011-02-22
    • US12605586
    • 2009-10-26
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • H01L21/44
    • H01L21/76898H01L23/481H01L2224/13H01L2224/13025H01L2224/14181
    • A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.
    • 在不降低包括通孔的半导体器件的可靠性的情况下,抑制穿通电极的脱落。 半导体器件100包括:硅衬底101; 穿过硅衬底101的通孔电极129; 以及设置在贯通电极129的侧面的周围并延伸穿过半导体基板101的第一绝缘环130.此外,半导体器件100还包括突出部分146,其设置在至少在 半导体衬底101的器件形成表面的背表面与通孔129接触,并沿着半导体衬底101的表面朝向通孔129的内部突出。
    • 5. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08456019B2
    • 2013-06-04
    • US13461230
    • 2012-05-01
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • H01L23/42H01L23/52
    • H01L21/76898H01L23/481H01L2224/13H01L2224/13025H01L2224/14181
    • A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.
    • 在不降低包括通孔的半导体器件的可靠性的情况下,抑制穿通电极的脱落。 半导体器件100包括:硅衬底101; 穿过硅衬底101的通孔电极129; 以及设置在贯通电极129的侧面的周围并延伸穿过半导体基板101的第一绝缘环130.此外,半导体器件100还包括突出部分146,其设置在至少在 半导体衬底101的器件形成表面的背表面与通孔129接触,并沿着半导体衬底101的表面朝向通孔129的内部突出。
    • 6. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08183685B2
    • 2012-05-22
    • US12986716
    • 2011-01-07
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • Masaya KawanoKoji SoejimaNobuaki Takahashi
    • H01L23/04H01L23/48
    • H01L21/76898H01L23/481H01L2224/13H01L2224/13025H01L2224/14181
    • A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.
    • 在不降低包括通孔的半导体器件的可靠性的情况下,抑制穿通电极的脱落。 半导体器件100包括:硅衬底101; 穿过硅衬底101的通孔电极129; 以及设置在贯通电极129的侧面的周围并延伸穿过半导体基板101的第一绝缘环130.此外,半导体器件100还包括突出部分146,其设置在至少在 半导体衬底101的器件形成表面的背表面与通孔129接触,并沿着半导体衬底101的表面朝向通孔129的内部突出。