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    • 2. 发明申请
    • Magnetoresistive Effect Head and Magnetic Recording/Playback Device
    • 磁阻效应头和磁记录/播放装置
    • US20100302688A1
    • 2010-12-02
    • US12784405
    • 2010-05-20
    • Masato ShiimotoKan YasuiNobuo YoshidaHiroyuki Takazawa
    • Masato ShiimotoKan YasuiNobuo YoshidaHiroyuki Takazawa
    • G11B5/127
    • G11B5/3932B82Y25/00G01R33/093G01R33/098H01L43/08H01L43/10
    • According to one embodiment, a magnetoresistive effect head includes a lower magnetic shield provided on a substrate, a magnetoresistive effect film laminated from a pinned layer with a pinned direction of magnetization, an intermediate layer, a free layer having a varying direction of magnetization controlled by an applied external magnetic field, a magnetic domain control layer formed with an intervening insulation layer on both sides in a track width direction of the magnetoresistive effect film, an upper magnetic shield, and electrodes for directing sense current flow in a direction perpendicular to a film surface of the magnetoresistive effect film, wherein a magnetic field applied by the magnetic domain control layer to a region away from an ABS of the free layer is at least 1.4 times larger than a magnetic field applied by the magnetic domain control layer to a region near the ABS of the free layer.
    • 根据一个实施例,磁阻效应头包括设置在基板上的下磁屏蔽,从具有钉扎方向的钉扎层层压的磁阻效应膜,中间层,具有变化的磁化方向的自由层, 施加的外部磁场,在磁阻效应膜的磁道宽度方向上在两侧形成有中间绝缘层的磁畴控制层,上磁屏蔽和用于引导垂直于膜的方向的感测电流的电极 磁阻效应膜的表面,其中由磁畴控制层施加到远离自由层的ABS的区域的磁场比由磁畴控制层施加到接近的区域的磁场的至少大1.4倍 ABS的自由层。
    • 4. 发明授权
    • Semiconductor device and electrical circuit device using thereof
    • 半导体装置及其电路装置
    • US07768066B2
    • 2010-08-03
    • US12179549
    • 2008-07-24
    • Hidekatsu OnoseHiroyuki Takazawa
    • Hidekatsu OnoseHiroyuki Takazawa
    • H01L29/94
    • H01L29/7828H01L25/18H01L29/0623H01L29/0696H01L29/1608H01L29/66068H01L29/7391H01L2924/0002H01L2924/00
    • A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.
    • UMOSFET能够降低阈值电压并产生大的饱和电流。 根据本发明的典型的UMOSFET包括:构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。
    • 10. 发明授权
    • High speed heterojunction bipolar transistor, and RF power amplifier and mobile communication system using the same
    • 高速异质结双极晶体管,射频功率放大器和移动通信系统使用相同
    • US06392258B1
    • 2002-05-21
    • US09516160
    • 2000-02-29
    • Koji HirataHiroyuki Takazawa
    • Koji HirataHiroyuki Takazawa
    • H01L29737
    • H01L29/66318H01L29/7371H03F3/195H03F3/60
    • To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter cap layer are successively formed in predetermined shapes a surface of a semi-insulating GaAs substrate, an inner edge part of a base electrode overlaps a periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer. The base electrode extends from the peripheral part of the emitter layer across the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode.
    • 为了提供超高速异质结双极晶体管,包括这种异质结双极晶体管的半导体器件具有其中以预定形状连续形成子集电极层,集电极层,基极层,发射极层(InGaP层)和发射极盖层的结构 半绝缘GaAs衬底的表面,基极的内边缘部分与发射极层的周边重叠,并且基极通过合金层与基底层电连接,所述合金层通过将发射极层合在基底 电极。 发射极层选择性地形成在基底层上。 基极从发射极层的周边部分穿过基底层延伸,合金层延伸到基底层的中间深度。 基层的边缘比基极的外边缘更靠内侧。