专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5917839A Apparatus and method for a read-modify-write operation in a dynamic random access memory 失效
标题翻译：在动态随机存取存储器中进行读 - 修改 - 写操作的装置和方法
公开(公告)号：US5917839A
公开(公告)日：1999-06-29
申请号：US863851
申请日：1997-05-27
申请人： Masashi Hashimoto , Anjana Ghosh
发明人： Masashi Hashimoto , Anjana Ghosh
IPC分类号： G06F11/10 , H03M13/09 , H03M13/00
CPC分类号： G06F11/1056 , H03M13/098
摘要： In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.
摘要翻译：在动态随机存取存储器单元10中，提供电路610-61N-1,615和617，其中在下一个连续时钟周期期间地址信号组的每个地址信号的不变化阻止了读取激活控制信号发送到存储器单元10.以这种方式，在读取 - 修改 - 写入操作的修改部分期间，存储器单元10不活动（即，不执行读取操作），使得操作中的潜在冲突避免了存储器单元10。

2. 发明授权

US6043686A Apparatus and method for transistor element reduction in circuits comparing serial data signals 失效
标题翻译：比较串行数据信号的电路中晶体管元件降低的装置和方法
公开(公告)号：US6043686A
公开(公告)日：2000-03-28
申请号：US861509
申请日：1997-05-22
申请人： Masashi Hashimoto , Anjana Ghosh
发明人： Masashi Hashimoto , Anjana Ghosh
IPC分类号： G06F7/02 , H03K19/096 , H03K19/21
CPC分类号： H03K19/215 , G06F7/02 , H03K19/0963
摘要： In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.
摘要翻译：在用于比较串行数据信号的集成电路的设计中，可以通过基于相关联的真值表实现比较门（12）而不是通过使用通用比较门分量来减少晶体管元件的数量。使用这种方法，可以使用两个晶体管元件（221,222）来实现异或门（22），可以使用两个晶体管元件（521,522），与门（62）222来实现异或门（52）可以使用单个晶体管元件（621）来实现，并且可以使用单个晶体管元件（721）来实现或门（72）。用于实现比较门的元件数量减少可以提供一个节省相关电路的晶体管元件。

3. 发明申请

US20050144582A1 Design techniques enabling storing of bit values which can change when the design changes 审中-公开
标题翻译：设计技术能够存储当设计改变时可能改变的位值
公开(公告)号：US20050144582A1
公开(公告)日：2005-06-30
申请号：US10988921
申请日：2004-11-15
申请人： Srinivasan Venkatraman , Anjana Ghosh , Sudheer Prasad , Shankar Kalyanasundaram
发明人： Srinivasan Venkatraman , Anjana Ghosh , Sudheer Prasad , Shankar Kalyanasundaram
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Techniques which allow a bit value stored/generated by integrated circuits to be changed by changing potentially only one of several masks used to fabricate the circuits. For example, when a single mask is to be re-designed to implement a design change (e.g., to fix minor bugs) and a version identifier is to be changed, the same mask can be used to implement the change in the version identifier as well. An embodiment allows the bit value to be changed any number of times by changing only one mask. As a result, the invention minimizes the number of masks that may need to be changed when implementing design changes.
摘要翻译：允许通过仅改变用于制造电路的多个掩模中的一个来改变由集成电路存储/生成的位值的技术。例如，当要重新设计单个掩码以实现设计更改（例如，修复较小的错误）并且要更改版本标识符时，可以使用相同的掩码来实现版本标识符的更改，如好。一个实施例允许通过仅改变一个掩码来改变位值任意次数。结果，本发明使实现设计改变时可能需要改变的掩模的数量最小化。

4. 发明授权

US06728320B1 Capacitive data and clock transmission between isolated ICs 有权
标题翻译：隔离IC之间的电容数据和时钟传输
公开(公告)号：US06728320B1
公开(公告)日：2004-04-27
申请号：US09637729
申请日：2000-08-11
申请人： Himamshu G. Khasnis , Anjana Ghosh , Krishnan Ramabhadran , Manoj S. Soman , Srinivasan Venkataraman
发明人： Himamshu G. Khasnis , Anjana Ghosh , Krishnan Ramabhadran , Manoj S. Soman , Srinivasan Venkataraman
IPC分类号： H04B300
CPC分类号： H04L25/0266 , H04L25/4904 , H04L25/4925
摘要： A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first capacitor and a second capacitor in parallel, linking a first circuit to a second circuit. First digital data is transferred from the first circuit to the second circuit, and a reference clock is provided by the first circuit and transmitted with the first data to the second circuit for recovery thereby. A first set of bi-level signals representing the zero values of the first data is applied to the first capacitor, such that a repeating level transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing the one values of the first data is applied to the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The clock and data are then recovered.
摘要翻译：一种用于在电容接口上传送数字数据的方法，包括一系列值和零值。该接口包括并联的第一电容器和第二电容器，将第一电路连接到第二电路。第一数字数据从第一电路传送到第二电路，并且参考时钟由第一电路提供并且与第一数据一起发送到第二电路以便恢复。表示第一数据的零值的第一组双电平信号被施加到第一电容器，使得参考时钟的重复电平转换对应于第一组双电平信号的第一电平转换。表示第一数据的一个值的第二组双电平信号被施加到第二电容器，使得参考时钟的重复转变对应于第二组双电平信号的第二电平转换。然后恢复时钟和数据。

5. 发明授权

US08842766B2 Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks 有权
标题翻译：使用多相时钟减少集成电路中的干扰信号的装置和方法
公开(公告)号：US08842766B2
公开(公告)日：2014-09-23
申请号：US12752082
申请日：2010-03-31
申请人： Indu Prathapan , Anjana Ghosh , Diganta Baishya , Sundarrajan Rangachari , Sankar Prasad Debnath , Ranjit Kumar Dash , Srinath Mathur Ramaswamy
发明人： Indu Prathapan , Anjana Ghosh , Diganta Baishya , Sundarrajan Rangachari , Sankar Prasad Debnath , Ranjit Kumar Dash , Srinath Mathur Ramaswamy
IPC分类号： G06F1/04 , G06F1/10 , G06F1/06 , H04B15/00 , H04B1/00 , H04L27/10 , H03D1/04
CPC分类号： G06F1/06 , G06F1/10
摘要： An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.
摘要翻译：一种使用多相时钟减少干扰信号的装置和方法。集成电路包括数字电路和模拟电路。数字电路包括导出的时钟电路，其被配置为接收具有频率D * f，D作为除数的根时钟，以将根时钟除以D，并且生成具有N个相位的多相时钟。数字电路的N个电路被配置为接收N个相位中的相应的一个，多相时钟的边沿分布在N个相位上。多相时钟引起由N电路从f至N * f和其谐波所减少的周期性峰值电流产生的干扰信号的频移。模拟电路接收带内范围的信号。 N值被配置为将干扰信号移动到信号的带内范围之外。

6. 发明申请

US20110241747A1 APPARATUS AND METHOD FOR REDUCING INTERFERENCE SIGNALS IN AN INTEGRATED CIRCUIT USING MULTIPHASE CLOCKS 有权
标题翻译：使用多相时钟降低集成电路干扰信号的装置和方法
公开(公告)号：US20110241747A1
公开(公告)日：2011-10-06
申请号：US12752082
申请日：2010-03-31
申请人： INDU PRATHAPAN , Anjana Ghosh , Diganta Baishya , Sundarrajan Rangachari , Sankar Prasad Debnath , Ranjit Kumar Dash , Srinath Mathur Ramaswamy
发明人： INDU PRATHAPAN , Anjana Ghosh , Diganta Baishya , Sundarrajan Rangachari , Sankar Prasad Debnath , Ranjit Kumar Dash , Srinath Mathur Ramaswamy
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , G06F1/10
摘要： An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.
摘要翻译：一种使用多相时钟减少干扰信号的装置和方法。集成电路包括数字电路和模拟电路。数字电路包括导出的时钟电路，其被配置为接收具有频率D * f，D作为除数的根时钟，以将根时钟除以D，并且生成具有N个相位的多相时钟。数字电路的N个电路被配置为接收N个相位中的相应的一个，多相时钟的边沿分布在N个相位上。多相时钟引起由N电路从f至N * f和其谐波所减少的周期性峰值电流产生的干扰信号的频移。模拟电路接收带内范围的信号。 N值被配置为将干扰信号移动到信号的带内范围之外。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式