专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06728320B1 Capacitive data and clock transmission between isolated ICs 有权
标题翻译：隔离IC之间的电容数据和时钟传输
公开(公告)号：US06728320B1
公开(公告)日：2004-04-27
申请号：US09637729
申请日：2000-08-11
申请人： Himamshu G. Khasnis , Anjana Ghosh , Krishnan Ramabhadran , Manoj S. Soman , Srinivasan Venkataraman
发明人： Himamshu G. Khasnis , Anjana Ghosh , Krishnan Ramabhadran , Manoj S. Soman , Srinivasan Venkataraman
IPC分类号： H04B300
CPC分类号： H04L25/0266 , H04L25/4904 , H04L25/4925
摘要： A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first capacitor and a second capacitor in parallel, linking a first circuit to a second circuit. First digital data is transferred from the first circuit to the second circuit, and a reference clock is provided by the first circuit and transmitted with the first data to the second circuit for recovery thereby. A first set of bi-level signals representing the zero values of the first data is applied to the first capacitor, such that a repeating level transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing the one values of the first data is applied to the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The clock and data are then recovered.
摘要翻译：一种用于在电容接口上传送数字数据的方法，包括一系列值和零值。该接口包括并联的第一电容器和第二电容器，将第一电路连接到第二电路。第一数字数据从第一电路传送到第二电路，并且参考时钟由第一电路提供并且与第一数据一起发送到第二电路以便恢复。表示第一数据的零值的第一组双电平信号被施加到第一电容器，使得参考时钟的重复电平转换对应于第一组双电平信号的第一电平转换。表示第一数据的一个值的第二组双电平信号被施加到第二电容器，使得参考时钟的重复转变对应于第二组双电平信号的第二电平转换。然后恢复时钟和数据。

2. 发明授权

US06992606B2 Method and circuit for multi-standard sigma-delta modulator 有权
标题翻译：多标准Σ-Δ调制器的方法和电路
公开(公告)号：US06992606B2
公开(公告)日：2006-01-31
申请号：US10865275
申请日：2004-06-10
申请人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
发明人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
IPC分类号： H03M1/20 , H03M3/00
CPC分类号： H03M7/3008 , H03M7/3011 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is configured to sum a difference between an input signal and an output of the sigma-delta modulator. A dithering circuit, also coupled to the signal input, is used to produce a dithering sequence. A summing point combines an output of the integrator and the dithering circuit while a quantizer converts the combined outputs into one of several discrete levels. The sigma-delta modulator further comprises a reset circuit to reset the sigma-delta modulator if the integrator becomes saturated. The sigma-delta modulator, as described, is compatible with G.Lite, ADSL, and ADSL+ variants of the digital subscriber line technical standards.
摘要翻译：用于多标准Σ-Δ调制器的系统和方法。优选实施例包括耦合到信号输入的积分器，其中积分器被配置为对输入信号和Σ-Δ调制器的输出之间的差进行求和。也耦合到信号输入端的抖动电路用于产生抖动序列。求和点将积分器和抖动电路的输出相结合，而量化器将组合的输出转换成几个离散电平之一。 Σ-Δ调制器还包括复位电路，以便在积分器变饱和时复位Σ-Δ调制器。所描述的Σ-Δ调制器与数字用户线技术标准的G.Lite，ADSL和ADSL +变体兼容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式