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1. 发明申请

US20100052171A1 CU WIRE IN SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF 审中-公开
标题翻译： CU线上半导体器件及其制造方法
公开(公告)号：US20100052171A1
公开(公告)日：2010-03-04
申请号：US12515538
申请日：2007-11-19
申请人： Hirotaka Ito , Takashi Onishi , Mikako Takeda , Masao Mizuno
发明人： Hirotaka Ito , Takashi Onishi , Mikako Takeda , Masao Mizuno
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： C22C9/00 , C23C14/024 , C23C14/165 , H01L21/2855 , H01L21/76843 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A Cu wire in a semiconductor device according to the present invention is a Cu wire embedded into wiring gutters or interlayer connective channels formed in an insulating film on a semiconductor substrate and the Cu wire comprises: a barrier layer comprising TaN formed on the wiring gutter side or the interlayer connective channel side; and a wire main body comprising Cu comprising one or more elements selected from the group consisting of Pt, In, Ti, Nb, B, Fe, V, Zr, Hf, Ga, Tl, Ru, Re, and Os in a total content of 0.05 to 3.0 atomic percent. The Cu wire in a semiconductor device according to the present invention is excellent in adhesiveness between the wire main body and the barrier layer.
摘要翻译：根据本发明的半导体器件中的Cu线是嵌入到形成在半导体衬底上的绝缘膜中的布线沟或层间连接沟道中的Cu线，并且所述Cu线包括：形成在布线槽侧的TaN的阻挡层或层间连接通道侧; 以及包含Cu，其包含选自Pt，In，Ti，Nb，B，Fe，V，Zr，Hf，Ga，Tl，Ru，Re和Os中的一种以上的元素，总含量为0.05〜3.0原子％。根据本发明的半导体器件中的Cu线在线主体和阻挡层之间的粘附性优异。

2. 发明申请

US20110147753A1 DISPLAY DEVICE, COPPER ALLOY FILM FOR USE THEREIN, AND COPPER ALLOY SPUTTERING TARGET 审中-公开
标题翻译：显示器件，铜合金膜及铜合金溅射靶
公开(公告)号：US20110147753A1
公开(公告)日：2011-06-23
申请号：US13056444
申请日：2009-08-14
申请人： Takashi Onishi , Aya Miki , Hiroshi Goto , Masao Mizuno , Hirotaka Ito , Katsufumi Tomihisa
发明人： Takashi Onishi , Aya Miki , Hiroshi Goto , Masao Mizuno , Hirotaka Ito , Katsufumi Tomihisa
IPC分类号： H01L29/04 , B32B17/06
CPC分类号： H01L23/53233 , C22C9/00 , C22C9/01 , H01L27/124 , H01L2924/0002 , Y10T428/265 , H01L2924/00
摘要： Disclosed is a Cu alloy film for a display device that has high adhesion to a glass substrate while maintaining a low electric resistance characteristic of Cu-based materials. The Cu alloy film is wiring in direct contact with a glass substrate on a board and contains 0.1 to 10.0 atomic % in total of one or more elements selected from the group consisting of Ti, Al, and Mg. Also disclosed is a display device comprising a thin-film transistor that comprises the Cu alloy film. In a preferred embodiment of the display device, the thin-film transistor has a bottom gate-type structure, and a gate electrode and scanning lines in the thin-film transistor comprise the Cu alloy film and are in direct contact with the glass substrate.
摘要翻译：公开了一种用于显示装置的Cu合金膜，其在保持Cu基材料的低电阻特性的同时对玻璃基板具有高粘附性。 Cu合金膜是与板上的玻璃基板直接接触的布线，并且含有0.1〜10.0原子％的一种以上选自Ti，Al，Mg的元素。还公开了包括包含Cu合金膜的薄膜晶体管的显示装置。在显示装置的优选实施例中，薄膜晶体管具有底栅型结构，并且薄膜晶体管中的栅电极和扫描线包括Cu合金膜并与玻璃基板直接接触。

3. 发明申请

US20110121459A1 SEMICONDUCTOR INTERCONNECTION 审中-公开
公开(公告)号：US20110121459A1
公开(公告)日：2011-05-26
申请号：US13003181
申请日：2009-07-10
申请人： Takashi Onishi , Masao Mizuno , Hirotaka Ito , Kazuyuki Kohama , Kazuhiro Ito , Susumu Tsukimoto , Masanori Murakami
发明人： Takashi Onishi , Masao Mizuno , Hirotaka Ito , Kazuyuki Kohama , Kazuhiro Ito , Susumu Tsukimoto , Masanori Murakami
IPC分类号： H01L23/535
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76867 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor interconnection wherein a barrier layer different from a TiO2 layer is formed on an interface between an insulating film and a Cu interconnection without increasing electrical resistivity of the Cu interconnection. In the semiconductor interconnection, a Cu interconnection containing Ti is embedded in a trench arranged on an insulating film on the semiconductor substrate, and a TiC layer is formed between the insulating film and the Cu interconnection. The insulating film is preferably composed of SiCO or SiCN. The thickness of the TiC layer is preferably 3-30 nm.
摘要翻译：提供了一种半导体互连，其中在绝缘膜和Cu互连之间的界面上形成不同于TiO 2层的阻挡层，而不增加Cu互连的电阻率。在半导体互连中，包含Ti的Cu互连嵌入设置在半导体衬底上的绝缘膜上的沟槽中，并且在绝缘膜和Cu互连之间形成TiC层。绝缘膜优选由SiCO或SiCN构成。 TiC层的厚度优选为3-30nm。

4. 发明申请

US20080014743A1 METHOD OF FABRICATING SEMICONDUCTOR INTERCONNECTIONS 失效
标题翻译：制造半导体互连的方法
公开(公告)号：US20080014743A1
公开(公告)日：2008-01-17
申请号：US11765006
申请日：2007-06-19
申请人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76867
摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
摘要翻译：提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且很深该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

5. 发明申请

US20070218690A1 FABRICATION METHOD FOR SEMICONDUCTOR INTERCONNECTIONS 有权
标题翻译：半导体互连的制造方法
公开(公告)号：US20070218690A1
公开(公告)日：2007-09-20
申请号：US11532796
申请日：2006-09-18
申请人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/44
CPC分类号： H01L21/76882 , H01L21/76843 , H01L21/76867 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.
摘要翻译：提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹部中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会导致电阻率的上升当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。

6. 发明申请

US20060068587A1 Copper alloy for semiconductor interconnections, fabrication method thereof, semiconductor device having copper alloy interconnections fabricated by the method, and sputtering target for fabricating copper alloy interconnections for semiconductors 有权
标题翻译：用于半导体互连的铜合金，其制造方法，通过该方法制造的具有铜合金互连的半导体器件，以及用于制造用于半导体的铜合金互连的溅射靶
公开(公告)号：US20060068587A1
公开(公告)日：2006-03-30
申请号：US11229721
申请日：2005-09-20
申请人： Masao Mizuno , Takashi Onishi
发明人： Masao Mizuno , Takashi Onishi
IPC分类号： H01L21/44
CPC分类号： H01L21/2855 , C22C9/00 , C23C14/165 , C23C14/3414 , C23C14/5806 , H01L21/76882
摘要： A Cu alloy for semiconductor interconnections contains at least one selected from the group consisting of 0.10 to 10 atomic percent of Sb, 0.010 to 1.0 atomic percent of Bi, and 0.01 to 3 atomic percent of Dy, with the balance being Cu and inevitable impurities. The Cu alloy can be reliably embedded in narrow trenches and/or via holes for interconnections.
摘要翻译：用于半导体互连的Cu合金含有选自由0.10〜10原子％的Sb，0.010〜1.0原子％的Bi和0.01〜3原子％的Dy，余量为Cu和不可避免的杂质的至少一种。 Cu合金可以可靠地嵌入狭窄的沟槽和/或用于互连的通孔中。

7. 发明授权

US4603208A Certain polyprenyl intermediates 失效
标题翻译：某些聚异戊烯中间体
公开(公告)号：US4603208A
公开(公告)日：1986-07-29
申请号：US465483
申请日：1983-02-10
申请人： Takashi Onishi , Shigeaki Suzuki , Fumio Mori , Tetsuo Takigawa , Yoshiji Fujita , Masao Mizuno , Takashi Nishida
发明人： Takashi Onishi , Shigeaki Suzuki , Fumio Mori , Tetsuo Takigawa , Yoshiji Fujita , Masao Mizuno , Takashi Nishida
IPC分类号： C07C69/767 , C07C317/00 , C07C317/24 , C07D213/70 , C07D213/71 , C07D309/12 , C07D317/18 , C07D405/12 , C07D417/12 , C07F7/18 , C07C69/78 , C07C147/103
CPC分类号： C07D405/12 , C07C317/00 , C07C321/00 , C07D309/12 , C07D317/18 , C07D417/12 , C07F7/1852
摘要： Novel polyprenyl compounds have the general formula: ##STR1## represents a cis-isoprene unit, n is an integer of 11-19, Z.sup.1 is --CH.sub.2 OH or a functional precursor thereof, and either one of R.sup.1 and R.sup.2 is a hydrogen atom and the other is --S(O).sub.m R.sup.3 in which m is an integer of 0 (zero), 1 or 2 and R.sup.3 is a phenyl, naphthyl, pyridyl or thiazolinyl group or such group substituted with at least one lower alkyl and/or halogen substituent. The topic novel polyprenyl compounds can be synthesized from derivatives of the polyprenol which is obtainable from leaves of Ginkgo biloba or Cedrus deodara, among others, by extraction, if necessary followed by hydrolytic treatment. The novel polyprenyl compounds can be converted to mammalian dolichols or precursors thereof by reductive elimination of the --S(O).sub.m R.sup.3 group.
摘要翻译：新颖的聚异戊二烯化合物具有以下通式：其中n为11〜19的整数，Z 1为-CH 2 OH的整数，或其功能性前体，R 1和R 2中的任一个是氢原子，另一个是-S（O）m R 3，其中m是0（0），1或2的整数，并且R 3是苯基，萘基，吡啶基或噻唑啉基或该基团被至少一个低级烷基和/或卤素取代基取代。主题新颖的聚异戊二烯基化合物可以由聚乙二醇的衍生物合成，其可以通过提取，如果需要然后进行水解处理，可以从银杏叶或塞德斯酵母的叶获得。新的聚异戊烯基化合物可以通过-S（O）m R 3基团的还原性消除而转化为哺乳动物多烯醇或其前体。

8. 发明授权

US07928573B2 Metal thin film for interconnection of semiconductor device 有权
标题翻译：用于半导体器件互连的金属薄膜
公开(公告)号：US07928573B2
公开(公告)日：2011-04-19
申请号：US11465626
申请日：2006-08-18
申请人： Takashi Onishi , Masao Mizuno , Mikako Takeda
发明人： Takashi Onishi , Masao Mizuno , Mikako Takeda
IPC分类号： H01L23/48
CPC分类号： H01L23/53233 , H01L21/2855 , H01L21/76882 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device. More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.
摘要翻译：提供了用于制造半导体器件的镶嵌互连的金属薄膜，其在高压退火期间表现出优异的高温流动性，并且可以制造具有低电阻和稳定高质量的半导体器件的互连。还提供了用于半导体器件的互连。更具体地说，一种用作半导体器件的互连的金属薄膜，其包含含有不小于0.4原子％至不大于2.0原子％的含有N的Cu合金; 以及通过在形成在半导体衬底上并形成有凹槽的绝缘体膜上形成金属薄膜而制造的半导体器件的互连，并且通过高压退火工艺在槽内填充金属薄膜被提供。

9. 发明授权

US07538027B2 Fabrication method for semiconductor interconnections 有权
标题翻译：半导体互连的制造方法
公开(公告)号：US07538027B2
公开(公告)日：2009-05-26
申请号：US11532796
申请日：2006-09-18
申请人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/4763
CPC分类号： H01L21/76882 , H01L21/76843 , H01L21/76867 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.
摘要翻译：提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹陷中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会引起电阻率的上升当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。

10. 发明授权

US07781339B2 Method of fabricating semiconductor interconnections 失效
标题翻译：制造半导体互连的方法
公开(公告)号：US07781339B2
公开(公告)日：2010-08-24
申请号：US11765006
申请日：2007-06-19
申请人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76867
摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
摘要翻译：提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且很深该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

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