专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08116894B2 Chemical mechanical polishing method and chemical mechanical polishing device 失效
标题翻译：化学机械抛光方法和化学机械抛光装置
公开(公告)号：US08116894B2
公开(公告)日：2012-02-14
申请号：US12340208
申请日：2008-12-19
申请人： Masanori Miyata , Taro Usami , Koichi Sogawa , Kenji Nishihara , Tadao Uehara , Shisyo Chin , Hiroaki Teratani , Akinori Suzuki , Yuuichi Kohno , Tetsuya Okada , Tohru Haruki
发明人： Masanori Miyata , Taro Usami , Koichi Sogawa , Kenji Nishihara , Tadao Uehara , Shisyo Chin , Hiroaki Teratani , Akinori Suzuki , Yuuichi Kohno , Tetsuya Okada , Tohru Haruki
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , B24B37/042 , H01L21/31053
摘要： A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . . , Tx represent the polishing time T required for achieving a target film thickness when performing the flattening process by polishing each of the interlayer insulating films coating the projecting patterns; and a step of calculating, with the use of a formula T=(R−b)/a, the polishing time T for the interlayer insulating films coating the projecting patterns having the area ratio R.
摘要翻译：一种化学机械抛光方法，包括形成多个层间绝缘膜以涂覆多个突起图案的步骤，所述多个突起图案中的至少一个形成在多个基板中的每一个上，由此所述多个突起图案相对于相应的基板具有不同的面积比R，并且在线性近似之前对层间绝缘膜进行平坦化处理; 获得表示面积比R和研磨时间T之间的关系的线性近似公式R = aT + b的步骤，其中R1，R2，R3，...。。。，Rx表示每个投影图案相对于相应基板的面积比R，以及T1，T2，T3。。。 Tx表示通过抛光涂覆突出图案的每个层间绝缘膜进行平坦化处理时达到目标膜厚所需的抛光时间T; 以及使用公式T =（R-b）/ a计算涂覆具有面积比R的投影图案的层间绝缘膜的研磨时间T的步骤。

2. 发明申请

US20090170323A1 CHEMICAL MECHANICAL POLISHING METHOD AND CHEMICAL MECHANICAL POLISHING DEVICE 失效
标题翻译：化学机械抛光方法和化学机械抛光装置
公开(公告)号：US20090170323A1
公开(公告)日：2009-07-02
申请号：US12340208
申请日：2008-12-19
申请人： MASANORI MIYATA , Taro Usami , Koichi Sogawa , Kenji Nishihara , Tadao Uehara , Shisyo Chin , Hiroaki Teratani , Akinori Suzuki , Yuuichi Kohno , Tetsuya Okada , Tohru Haruki
发明人： MASANORI MIYATA , Taro Usami , Koichi Sogawa , Kenji Nishihara , Tadao Uehara , Shisyo Chin , Hiroaki Teratani , Akinori Suzuki , Yuuichi Kohno , Tetsuya Okada , Tohru Haruki
IPC分类号： H01L21/304
CPC分类号： H01L22/20 , B24B37/042 , H01L21/31053
摘要： A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . . , Tx represent the polishing time T required for achieving a target film thickness when performing the flattening process by polishing each of the interlayer insulating films coating the projecting patterns; and a step of calculating, with the use of a formula T=(R−b)/a, the polishing time T for the interlayer insulating films coating the projecting patterns having the area ratio R.
摘要翻译：一种化学机械抛光方法，包括形成多个层间绝缘膜以涂覆多个突起图案的步骤，所述多个突起图案中的至少一个形成在多个基板中的每一个上，由此所述多个突起图案相对于相应的基板具有不同的面积比R，并且在线性近似之前对层间绝缘膜进行平坦化处理; 获得表示面积比R和研磨时间T之间的关系的线性近似公式R = aT + b的步骤，其中R1，R2，R3，...。。。，Rx表示每个投影图案相对于相应基板的面积比R，以及T1，T2，T3。。。 Tx表示通过抛光涂覆突出图案的每个层间绝缘膜进行平坦化处理时达到目标膜厚所需的抛光时间T; 以及使用公式T =（R-b）/ a计算涂覆具有面积比R的投影图案的层间绝缘膜的研磨时间T的步骤。

3. 发明授权

US07755207B2 Wafer, reticle, and exposure method using the wafer and reticle 失效
标题翻译：使用晶片和掩模版的晶片，掩模版和曝光方法
公开(公告)号：US07755207B2
公开(公告)日：2010-07-13
申请号：US11363841
申请日：2006-02-28
申请人： Koichi Sogawa , Kiyoshi Yano , Tohru Haruki , Hidetsugu Miyake , Shouji Tochishita , Minoru Ohtomo , Kenji Nishihara
发明人： Koichi Sogawa , Kiyoshi Yano , Tohru Haruki , Hidetsugu Miyake , Shouji Tochishita , Minoru Ohtomo , Kenji Nishihara
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7084 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.
摘要翻译：公开了一种半导体晶片，其包括基板; 形成在所述基板上的多个器件芯片区域; 在基板上形成为格子状的多个划痕线，划线被设置为将装置芯片区域彼此分开; 形成由用于半导体晶片对准的金属膜形成的至少一个对准标记的空白区域，所述空白区域设置在与所述器件芯片区域不同的区域中; 以及防止对准标记存在的划片区域，划线区域设置在空白区域穿过划线的每个区域中。

4. 发明申请

US20070023932A1 Wafer, reticle, and exposure method using the wafer and reticle 失效
标题翻译：使用晶片和掩模版的晶片，掩模版和曝光方法
公开(公告)号：US20070023932A1
公开(公告)日：2007-02-01
申请号：US11363841
申请日：2006-02-28
申请人： Koichi Sogawa , Kiyoshi Yano , Tohru Haruki , Hidetsugu Miyake , Shouji Tochishita , Minoru Ohtomo , Kenji Nishihara
发明人： Koichi Sogawa , Kiyoshi Yano , Tohru Haruki , Hidetsugu Miyake , Shouji Tochishita , Minoru Ohtomo , Kenji Nishihara
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7084 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.
摘要翻译：公开了一种半导体晶片，其包括基板; 形成在所述基板上的多个器件芯片区域; 在基板上形成为格子状的多个划痕线，划线被设置为将装置芯片区域彼此分开; 形成由用于半导体晶片对准的金属膜形成的至少一个对准标记的空白区域，所述空白区域设置在与所述器件芯片区域不同的区域中; 以及防止对准标记存在的划片区域，划线区域设置在空白区域穿过划线的每个区域中。

5. 发明申请

US20100262943A1 EFFICIENT PROVISION OF ALIGNMENT MARKS ON SEMICONDUCTOR WAFER 有权
标题翻译：在半导体波形上有效地提供对准标记
公开(公告)号：US20100262943A1
公开(公告)日：2010-10-14
申请号：US12703405
申请日：2010-02-10
申请人： Koichi Sogawa
发明人： Koichi Sogawa
IPC分类号： G06F17/50
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.
摘要翻译：半导体晶片包括多个芯片区域，每个芯片区域包括两个或更多个器件芯片区域，并且沿X轴方向和Y轴方向布置，多个划线形成为平行于X轴和Y轴，以便将设备芯片区域以及在包括在一个多芯片区域中的相邻设备芯片区域之间的划线上的每个多芯片区域中形成的一个或多个对准标记，所述一个或多个对准标记少于每个多芯片区域中的器件芯片面积并用于半导体晶片的定位。

6. 发明授权

US08043928B2 Efficient provision of alignment marks on semiconductor wafer 有权
标题翻译：在半导体晶圆上有效提供对准标记
公开(公告)号：US08043928B2
公开(公告)日：2011-10-25
申请号：US12703405
申请日：2010-02-10
申请人： Koichi Sogawa
发明人： Koichi Sogawa
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.
摘要翻译：半导体晶片包括多个芯片区域，每个芯片区域包括两个或更多个器件芯片区域，并且沿X轴方向和Y轴方向布置，多个划线形成为平行于X轴和Y轴，以便将设备芯片区域以及在包括在一个多芯片区域中的相邻设备芯片区域之间的划线上的每个多芯片区域中形成的一个或多个对准标记，所述一个或多个对准标记少于每个多芯片区域中的器件芯片面积并用于半导体晶片的定位。

7. 发明授权

US06558859B2 Method of checking pattern measurement and image recognition assisting pattern 有权
标题翻译：检查图案测量和图像识别辅助图案的方法
公开(公告)号：US06558859B2
公开(公告)日：2003-05-06
申请号：US09851096
申请日：2001-05-09
申请人： Koichi Sogawa
发明人： Koichi Sogawa
IPC分类号： G03F900
CPC分类号： H01L22/34
摘要： A method of detecting a position of a size check pattern on a substrate by using a size check apparatus so as to measure a size of the size check pattern for a purpose of checking precision of production, comprising the steps of a) providing image recognition assisting patterns on the substrate on both sides of a portion to be measured of the size check pattern, b) setting the size check apparatus to have an image recognition area that includes both the size check pattern and the image recognition assisting patterns, and c) detecting the position of the size check pattern by use of the size check apparatus based on the size check pattern and the image recognition assisting patterns.
摘要翻译：一种通过使用尺寸检查装置来检测尺寸检查图案在基板上的位置的方法，以便测量尺寸检查图案的尺寸以便检查生产精度，包括以下步骤：a）提供图像识别辅助 b）将尺寸检查装置设置为具有包括尺寸检查图案和图像识别辅助图案两者的图像识别区域，以及c）检测尺寸检查图案的图像识别区域基于尺寸检查图案和图像识别辅助图案使用尺寸检查装置的尺寸检查图案的位置。

8. 发明授权

US5670402A Method of manufacturing core implanted semiconductor devices 失效
标题翻译：核心注入半导体器件的制造方法
公开(公告)号：US5670402A
公开(公告)日：1997-09-23
申请号：US498885
申请日：1995-07-06
申请人： Koichi Sogawa , Yuichi Ando
发明人： Koichi Sogawa , Yuichi Ando
IPC分类号： G11C17/08 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/108 , H01L27/112
CPC分类号： H01L27/112 , H01L27/1126
摘要： In a semiconductor device, N-type diffusion regions for providing an LDD structure are formed on a P-type substrate. A thick CVD deposited insulating film is formed on both the diffusion regions. A word line layer is formed on this deposited insulating film and a gate oxide film in a direction crossing the diffusion regions. Since the deposited insulating film is set to be thick, a capacity between one of the diffusion regions as a bit line layer and the word line layer is reduced so that a reading speed of the semiconductor device is improved. Further, a punch through proof pressure is increased since the diffusion regions have an LDD structure. Thus, it is possible to provide a planar cell structure which increases the reading speed and is advantageous in a fine structure. Another semiconductor device is also shown. A method for manufacturing the semiconductor device is further shown.
摘要翻译：在半导体器件中，在P型衬底上形成用于提供LDD结构的N型扩散区。在两个扩散区上形成厚的CVD沉积绝缘膜。在该淀积绝缘膜上形成字线层，并在与扩散区交叉的方向上形成栅极氧化膜。由于沉积的绝缘膜被设定为较厚，所以作为位线层的一个扩散区域和字线层之间的电容减小，从而提高了半导体器件的读取速度。此外，由于扩散区域具有LDD结构，因此穿孔证明压力增加。因此，可以提供增加读取速度并且在精细结构中有利的平面单元结构。还示出了另一半导体器件。进一步示出了制造半导体器件的方法。

9. 发明授权

US5362662A Method for producing semiconductor memory device having a planar cell structure 失效
标题翻译：具有平面单元结构的半导体存储器件的制造方法
公开(公告)号：US5362662A
公开(公告)日：1994-11-08
申请号：US57188
申请日：1993-05-03
申请人： Yuichi Ando , Koichi Sogawa
发明人： Yuichi Ando , Koichi Sogawa
IPC分类号： H01L27/112 , H01L21/70 , H01L27/00
CPC分类号： H01L27/112
摘要： A semiconductor memory device includes a substrate, a first diffusion region composed of at least one longitudinal and continuous source region which is disposed on the substrate and commonly used for a plurality of memory transistors, and a second diffusion region composed of at least one longitudinal and continuous drain region which is disposed in parallel with the first diffusion region and commonly used for the plurality of memory transistors. A refractory metal film is disposed on each of the first and second diffusion regions. An electric insulation film is disposed on the refractory metal film. A plurality of parallel gate electrodes are disposed crossing over the first and second diffusion regions. And a gate oxide film is arranged to electrically insulate the gate electrodes from the diffusion regions.
摘要翻译：半导体存储器件包括衬底，由至少一个纵向和连续源极区域构成的第一扩散区域，该第一扩散区域设置在衬底上并且通常用于多个存储晶体管，第二扩散区域由至少一个纵向和连续漏极区域，其与第一扩散区域平行设置并且共同用于多个存储晶体管。难熔金属膜设置在第一和第二扩散区域中的每一个上。电绝缘膜设置在难熔金属膜上。多个平行栅电极被布置成跨越第一和第二扩散区。并且栅极氧化膜被布置成使栅电极与扩散区电绝缘。

10. 发明授权

US07692319B2 Efficient provision of alignment marks on semiconductor wafer 失效
标题翻译：在半导体晶圆上有效提供对准标记
公开(公告)号：US07692319B2
公开(公告)日：2010-04-06
申请号：US11529621
申请日：2006-09-28
申请人： Koichi Sogawa
发明人： Koichi Sogawa
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.
摘要翻译：半导体晶片包括多个芯片区域，每个芯片区域包括两个或更多个器件芯片区域，并且沿X轴方向和Y轴方向布置，多个划片线形成为平行于X轴和Y轴，以便将设备芯片区域以及在包括在一个多芯片区域中的相邻设备芯片区域之间的划线上的每个多芯片区域中形成的一个或多个对准标记，所述一个或多个对准标记少于每个多芯片区域中的器件芯片面积并用于半导体晶片的定位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式