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1. 发明申请

US20130288133A1 POROUS MEMBRANE AND PROCESS FOR PREPARING THE SAME 审中-公开
标题翻译：多孔膜及其制备方法
公开(公告)号：US20130288133A1
公开(公告)日：2013-10-31
申请号：US13977322
申请日：2012-10-12
申请人： Masanori Imai , Satoshi Nemoto
发明人： Masanori Imai , Satoshi Nemoto
IPC分类号： H01G9/02 , B29D99/00 , B29C44/02 , H01M2/16
CPC分类号： H01G9/02 , B29C44/02 , B29D99/005 , C08L1/02 , D04H1/425 , D21H11/00 , D21H11/16 , D21H15/02 , D21H27/08 , H01M2/145 , H01M2/1626 , H01M10/052
摘要： The present invention relates to a porous membrane including cellulose fibers, wherein the cellulose fibers are obtained from a mixture of more than 50% by weight of (1) first raw material cellulose fibers having a surface area determined by congo red coloring of 250 m2/g or more and 500 m2/g or less; and less than 50% by weight of (2) second raw material cellulose fibers having a surface area determined by congo red coloring of 150 m2/g or more and less than 250 m2/g. The porous membrane according to the present invention can provide a separator for electrochemical devices with superior properties, at a reasonable cost.
摘要翻译：本发明涉及一种包括纤维素纤维的多孔膜，其中纤维素纤维由大于50重量％的（1）第一原料纤维素纤维的混合物获得，所述第一原料纤维素纤维具有通过刚果红色着色确定的表面积为250m 2 / g以上500m 2 / g以下; 和小于50重量％的（2）具有150m 2 / g以上且小于250m 2 / g的刚果红色表示的表面积的第二原料纤维素纤维。根据本发明的多孔膜可以以合理的成本提供具有优异性能的电化学装置的隔膜。

2. 发明申请

US20130280615A1 POROUS MEMBRANE AND PROCESS FOR PREPARING THE SAME 有权
标题翻译：多孔膜及其制备方法
公开(公告)号：US20130280615A1
公开(公告)日：2013-10-24
申请号：US13978342
申请日：2012-10-12
申请人： Masanori Imai , Satoshi Nemoto
发明人： Masanori Imai , Satoshi Nemoto
IPC分类号： H01M2/16 , B29C44/22 , H01G9/02
CPC分类号： H01M2/16 , B29C44/22 , C08J5/2212 , C08J2301/02 , C08K5/00 , C08L1/02 , C08L1/286 , C08L2205/02 , C08L2205/16 , H01G9/02 , H01M2/145 , H01M2/1626 , H01M10/0525 , Y02E60/122 , Y02P70/54
摘要： The present invention relates to a porous membrane containing cellulose fibers, wherein the cellulose fibers contain 5% by weight or more of cellulose fibers with a diameter of 1 μm or more, relative to the total weight of the cellulose, and the porous membrane has a tensile strength of 50 N·m/g or more, and/or has a tear strength of 0.40 kN/m or more. The porous membrane according to the present invention can provide a separator for electrochemical devices with superior properties, at a reasonable cost.
摘要翻译：本发明涉及含有纤维素纤维的多孔膜，其中纤维素纤维相对于纤维素的总重量含有5重量％以上的直径为1μm以上的纤维素纤维，多孔膜具有拉伸强度为50N·m / g以上，和/或具有0.40kN / m以上的撕裂强度。根据本发明的多孔膜可以以合理的成本提供具有优异性能的电化学装置的隔膜。

3. 发明申请

US20130280616A1 POROUS MEMBRANE AND PROCESS FOR PREPARING THE SAME 有权
标题翻译：多孔膜及其制备方法
公开(公告)号：US20130280616A1
公开(公告)日：2013-10-24
申请号：US13978352
申请日：2012-10-12
申请人： Yoshiharu Machii , Satoshi Nemoto , Yohta Mori
发明人： Yoshiharu Machii , Satoshi Nemoto , Yohta Mori
IPC分类号： H01M2/16 , H01G11/52 , H01G9/004 , H01M2/14
CPC分类号： H01M2/16 , H01G9/004 , H01G9/02 , H01G11/52 , H01M2/145 , H01M2/1626 , H01M10/0525 , Y02E60/13 , Y02T10/7022
摘要： The present invention relates to a porous membrane containing cellulose fibers, wherein the cellulose fibers contain 5% by weight or more of cellulose fibers with a diameter of 1 μm or more, relative to the total weight of the cellulose fibers, the mode diameter (maximal frequency) of the pore distribution determined by the mercury penetration method is less than 0.3 μm, the air resistance per thickness of 10 μm is from 20 to 600 seconds, and the porous membrane has a volume resistivity of 1500 Ω·cm or less determined by alternate current with a frequency of 20 kHz in which the porous membrane is impregnated with 1 mol/LiPF6/propylene carbonate solution. The porous membrane according to the present invention can provide a separator for electrochemical devices with superior properties at a reasonable cost.
摘要翻译：本发明涉及含有纤维素纤维的多孔膜，其中纤维素纤维相对于纤维素纤维的总重量含有5重量％以上的直径为1μm以上的纤维素纤维，模式直径（最大值频率）通过水银渗透法测定的孔分布小于0.3μm，10μm厚度的空气阻力为20〜600秒，多孔膜的体积电阻率为1500Ω·cm以下，由频率为20kHz的交流电流，其中多孔膜用1mol / LiPF 6 /碳酸丙烯酯溶液浸渍。根据本发明的多孔膜可以以合理的成本提供具有优异性能的电化学装置用隔膜。

4. 发明授权

US07904677B2 Memory control device 有权
标题翻译：内存控制装置
公开(公告)号：US07904677B2
公开(公告)日：2011-03-08
申请号：US12230252
申请日：2008-08-26
申请人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
发明人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.
摘要翻译：一种可以提高存储器接口速度的存储器控制装置。分组分解部分将分组数据分解成分段并检测分组质量信息。存储器管理部分具有地址管理表，并根据分组质量信息管理分组数据被存储的状态。分段/请求信息反汇编器通过访问单元将段分解成数据，通过该存取单元可以写入/读取存储器，并根据访问单元生成写入请求和读取请求。存储器访问控制器避免由于存储体约束而被禁止的存储体存取，从写入请求或所生成的读取请求中提取与可访问存储体相对应的写入请求或读取请求，并且获得对存储器的写入/读取访问。

5. 发明申请

US20100046534A1 DATA TRANSMISSION APPARATUS 审中-公开
标题翻译：数据传输设备
公开(公告)号：US20100046534A1
公开(公告)日：2010-02-25
申请号：US12545899
申请日：2009-08-24
申请人： Hiroshi KUROSAKI , Satoshi Nemoto , Hideo Abe
发明人： Hiroshi KUROSAKI , Satoshi Nemoto , Hideo Abe
IPC分类号： H04L12/56
CPC分类号： H04L49/552 , H04L47/50 , H04L49/1523 , H04L49/3072 , H04L49/90 , H04L49/9094
摘要： A data transmission apparatus includes an input interface; an output interface; and a first and second switch portions which are provided between the input interface and the output interface and which transfer a frame from the input interface to a destination output interface, wherein the first and the second switch portions each include a buffer which stores the frame from the input interface according to the destination output interface, a scheduler which reads the frame from the buffer and transfers the frame to the destination output interface, and a frame amount detection portion which detects the amount of frames held in the buffer according to the destination output interface, and the scheduler controls reading from the buffer based on difference between the held frame amount of the first switch portion and the held frame amount of the second switch portion which is detected by the frame amount detection portion.
摘要翻译：数据传输装置包括输入接口; 输出接口; 以及第一和第二开关部分，其设置在所述输入接口和所述输出接口之间，并且将帧从所述输入接口传送到目的地输出接口，其中所述第一和第二开关部分各自包括缓冲器，所述缓冲器存储来自根据目的地输出接口的输入接口，从缓冲器读取帧并将帧传送到目的地输出接口的调度器，以及根据目的地输出检测保存在缓冲器中的帧量的帧量检测部分接口，并且调度器基于由第一开关部分的保持帧量和由帧量检测部分检测到的第二开关部分的保持帧量之间的差异来控制从缓冲器的读取。

6. 发明授权

US09495256B2 Apparatus and method for switching a packet 有权
标题翻译：用于切换分组的装置和方法
公开(公告)号：US09495256B2
公开(公告)日：2016-11-15
申请号：US13595224
申请日：2012-08-27
申请人： Kazuto Nishimura , Hideo Abe , Satoshi Nemoto
发明人： Kazuto Nishimura , Hideo Abe , Satoshi Nemoto
IPC分类号： H04L12/26 , G06F11/20 , H04L12/851 , H04L12/64 , H04L12/875 , H04L12/863 , H04L12/933 , H04L12/861
CPC分类号： G06F11/2005 , H04L12/6418 , H04L47/24 , H04L47/56 , H04L47/6215 , H04L49/15 , H04L49/90
摘要： An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.
摘要翻译：一种装置包括处于待机模式的第一开关电路和处于待机模式的第二开关电路。该设备接收高优先级的报文和低优先级的报文。每个开关电路分别将高优先级分组和低优先级分组存储到第一和第二缓冲器中。每个开关电路执行分组读出处理，从第一和第二缓冲器读出分组，其中在第一缓冲器上优先执行分组读出处理。当从第一开关电路输出的低优先级分组被确定为：第一开关电路时，随着高优先级分组发送的数据量的增加，高优先级分组的背压时间变长，是在第一时间接收到的分组，该分组晚于在第二时间接收到从第二开关电路输出的另一低优先级分组的分组。

7. 发明授权

US08594092B2 Packet relay method and device 有权
标题翻译：分组中继方法和设备
公开(公告)号：US08594092B2
公开(公告)日：2013-11-26
申请号：US11959615
申请日：2007-12-19
申请人： Satoshi Nemoto , Hiroshi Tomonaga , Akihiro Hata
发明人： Satoshi Nemoto , Hiroshi Tomonaga , Akihiro Hata
IPC分类号： H04L12/28
CPC分类号： H04L49/552 , H04L49/1515 , H04L49/205
摘要： In a packet relay method and device which can reduce a congestion of switching even when segment data are concentrated, segment data dividing portions respectively extract a destination address and a packet length from received packets, divide the packets into predetermined length data based on each packet length, and generates location information indicating locations in the packets respectively for the data. The segment data dividing portions add segment headers in which the location information, the destination address, and an address of its own device as a source address are set are added to each of the data, generate segment data, and provide the segment data to switches within a switch card in parallel.
摘要翻译：在分组中继方法和装置中，即使在分段数据集中的情况下也可以减少切换拥塞，分段数据分割部分从接收到的分组分别提取目的地址和分组长度，根据每个分组长度将分组划分成预定长度的数据并分别产生指示数据包中的位置的位置信息。分段数据分割部分添加分段报头，其中设置作为源地址的其自身设备的位置信息，目的地址和地址被设置为每个数据，生成分段数据，并将分段数据提供给切换在开关卡内并行。

8. 发明申请

US20090172318A1 Memory control device 有权
标题翻译：内存控制装置
公开(公告)号：US20090172318A1
公开(公告)日：2009-07-02
申请号：US12230252
申请日：2008-08-26
申请人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
发明人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F13/1689
摘要： A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.
摘要翻译：一种可以提高存储器接口速度的存储器控制装置。分组分解部分将分组数据分解成分段并检测分组质量信息。存储器管理部分具有地址管理表，并根据分组质量信息管理分组数据被存储的状态。分段/请求信息反汇编器通过访问单元将段分解成数据，通过该存取单元可以写入/读取存储器，并根据访问单元生成写入请求和读取请求。存储器访问控制器避免由于存储体约束而被禁止的存储体存取，从写入请求或所生成的读取请求中提取与可访问存储体相对应的写入请求或读取请求，并且获得对存储器的写入/读取访问。

9. 发明授权

US08730792B2 Switching device and switching method 有权
标题翻译：开关器件和开关方式
公开(公告)号：US08730792B2
公开(公告)日：2014-05-20
申请号：US13036227
申请日：2011-02-28
申请人： Satoshi Nemoto , Yukio Suda
发明人： Satoshi Nemoto , Yukio Suda
IPC分类号： G01R31/08
CPC分类号： H04L49/505 , H04L47/11 , H04L47/283 , H04L49/1515
摘要： Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.
摘要翻译：包括在切换装置中的第一切换处理器和第二切换处理器各自将多条数据切换到确定的目的地。控制器根据第一交换处理器的拥塞状态旁路 - 将由第一交换处理器接收的确定数量的数据发送到第二交换处理器，以使第一交换处理器和第二交换处理器都执行切换处理。或者，控制器根据第二交换处理器的拥塞状态，将由第二交换处理器接收的确定数量的数据发送到第一交换处理器，以使第一交换处理器和第二交换处理器都执行切换过程。

10. 发明申请

US20100284862A1 CLEANING EQUIPMENT AND ANALYZER 审中-公开
标题翻译：清洁设备和分析仪
公开(公告)号：US20100284862A1
公开(公告)日：2010-11-11
申请号：US12840075
申请日：2010-07-20
申请人： Kenichi Kakizaki , Shinichi Inamura , Satoshi Nemoto
发明人： Kenichi Kakizaki , Shinichi Inamura , Satoshi Nemoto
IPC分类号： A47L7/00 , G01N21/00
CPC分类号： G01N35/1004 , G01N35/1016 , G01N2035/1018
摘要： An analyzer (1) comprises: a detecting section (254) for continuously detecting the capacitance between an electrode (253) provided in a nozzle cleaning tank (252) and a suction nozzle (251b) ; a determining section (45) for determining whether the suction nozzle (251b) is clogged or not based on the time dependency of capacitance detected at the detecting section (254), that is the time dependency of capacitance between the suction nozzle (251b), which is raised out of the nozzle cleaning tank (252) after BF cleaning liquid (Lw) is sucked, and the electrode (253); and a controlling section (41) for stopping the discharge of the BF cleaning liquid from an discharge nozzle (251a) into a reaction tube (10) when it is determined by the determining section (45) that the suction nozzle (251b) is clogged.
摘要翻译：分析器（1）包括：用于连续地检测设置在喷嘴清洁罐（252）中的电极（253）和吸嘴（251b）之间的电容的检测部分（254）; 基于在检测部分（254）检测到的电容的时间依赖性，确定吸嘴（251b）是否堵塞的确定部分（45），即吸嘴（251b），在BF清洗液（Lw）被吸引之后从喷嘴清洗槽252升出，电极253。以及控制部（41），其在由所述判定部（45）判定为所述吸嘴（251b）堵塞时，停止从所述排出喷嘴（251a）排出到所述反应管（10）的排出口。

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