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1. 发明授权

US08730792B2 Switching device and switching method 有权
标题翻译：开关器件和开关方式
公开(公告)号：US08730792B2
公开(公告)日：2014-05-20
申请号：US13036227
申请日：2011-02-28
申请人： Satoshi Nemoto , Yukio Suda
发明人： Satoshi Nemoto , Yukio Suda
IPC分类号： G01R31/08
CPC分类号： H04L49/505 , H04L47/11 , H04L47/283 , H04L49/1515
摘要： Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.
摘要翻译：包括在切换装置中的第一切换处理器和第二切换处理器各自将多条数据切换到确定的目的地。控制器根据第一交换处理器的拥塞状态旁路 - 将由第一交换处理器接收的确定数量的数据发送到第二交换处理器，以使第一交换处理器和第二交换处理器都执行切换处理。或者，控制器根据第二交换处理器的拥塞状态，将由第二交换处理器接收的确定数量的数据发送到第一交换处理器，以使第一交换处理器和第二交换处理器都执行切换过程。

2. 发明申请

US20110292806A1 SWITCHING DEVICE AND SWITCHING METHOD 有权
标题翻译：切换设备和切换方法
公开(公告)号：US20110292806A1
公开(公告)日：2011-12-01
申请号：US13036227
申请日：2011-02-28
申请人： Satoshi NEMOTO , Yukio SUDA
发明人： Satoshi NEMOTO , Yukio SUDA
IPC分类号： H04L12/56
CPC分类号： H04L49/505 , H04L47/11 , H04L47/283 , H04L49/1515
摘要： Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.
摘要翻译：包括在切换装置中的第一切换处理器和第二切换处理器各自将多条数据切换到确定的目的地。控制器根据第一交换处理器的拥塞状态旁路 - 将由第一交换处理器接收的确定数量的数据发送到第二交换处理器，以使第一交换处理器和第二交换处理器都执行切换处理。或者，控制器根据第二交换处理器的拥塞状态，将由第二交换处理器接收的确定数量的数据发送到第一交换处理器，以使第一交换处理器和第二交换处理器都执行切换过程。

3. 发明授权

US07978704B2 Frame buffer monitoring method and device 有权
标题翻译：帧缓冲区监控方法和设备
公开(公告)号：US07978704B2
公开(公告)日：2011-07-12
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/28
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译：在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较读取，以及期望信息是否与关于帧的信息一致。作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如，被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。此外，初始化FIFO缓冲器的写目的地地址和读源地址。

4. 发明申请

US20070189314A1 Frame buffer monitoring method and device 有权
标题翻译：帧缓冲区监控方法和设备
公开(公告)号：US20070189314A1
公开(公告)日：2007-08-16
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/56
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译：在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较读取，以及期望信息是否与关于帧的信息一致。作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如，被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。此外，初始化FIFO缓冲器的写目的地地址和读源地址。

5. 发明授权

US06587459B1 Time slot assignment circuit 有权
标题翻译：时隙分配电路
公开(公告)号：US06587459B1
公开(公告)日：2003-07-01
申请号：US09272503
申请日：1999-03-19
申请人： Yukio Suda , Satoshi Nemoto , Masahiro Shioda , Takashi Kuwabara
发明人： Yukio Suda , Satoshi Nemoto , Masahiro Shioda , Takashi Kuwabara
IPC分类号： H04L1250
CPC分类号： H04Q11/0421
摘要： A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.
摘要翻译：一个TSA电路，从超高速环网接收上位输入的传输数据，从高速环网接收低端的传输数据，并将上位传出数据输出到超高速环网和下侧传输传输向高速环网提供数据，具有时隙分配功能块，具有时间切换和空间切换，并且产生通过以比特为单位的输入传输数据的切换通道获得的输出传输数据，由此高速和大容量输入传输数据可以被处理用于时隙分配（TSA），在信道中互换，并作为输出传输数据通过相对小的电路配置发送出去。

6. 发明授权

US07463169B2 64B/66B Encoding data generation method and circuit 有权
标题翻译： 64B / 66B编码数据生成方法和电路
公开(公告)号：US07463169B2
公开(公告)日：2008-12-09
申请号：US11877831
申请日：2007-10-24
申请人： Masayuki Horie , Yukio Suda
发明人： Masayuki Horie , Yukio Suda
IPC分类号： H03M7/00
CPC分类号： H03M7/04
摘要： In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
摘要翻译：在用于64B / 66B编码的更有效的数据生成方法和电路中，当分组数据和数据分组的头尾信息被接收时，写入将头尾识别字节分别添加到头部的用户数据，基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。从预定地址，按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。在不能进行读取的期间，8n字节（n> = 1）的空闲字节和指示空闲字节的控制数据，或8n字节（n> = 2）的维护用户数据，其中头和尾识别字节分别被添加到维护信息的头部和尾部，并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。

7. 发明申请

US20080100481A1 64B/66B Encoding Data Generation Method and Circuit 有权
标题翻译： 64B / 66B编码数据生成方法与电路
公开(公告)号：US20080100481A1
公开(公告)日：2008-05-01
申请号：US11877831
申请日：2007-10-24
申请人： Masayuki Horie , Yukio Suda
发明人： Masayuki Horie , Yukio Suda
IPC分类号： H03M5/00
CPC分类号： H03M7/04
摘要： In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
摘要翻译：在用于64B / 66B编码的更有效的数据生成方法和电路中，当分组数据和数据分组的头尾信息被接收时，写入将头尾识别字节分别添加到头部的用户数据，基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。从预定地址，按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。在不能进行读取的期间，8n字节（n> = 1）的空闲字节和指示空闲字节的控制数据，或8n字节（n> = 2）的维护用户数据，其中头和尾识别字节分别被添加到维护信息的头部和尾部，并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。

8. 发明授权

US5014271A Pulse insertion circuit 失效
标题翻译：脉冲插入电路
公开(公告)号：US5014271A
公开(公告)日：1991-05-07
申请号：US323944
申请日：1989-03-15
申请人： Naonobu Fujimoto , Yukio Suda , Katsutoshi Miyaji
发明人： Naonobu Fujimoto , Yukio Suda , Katsutoshi Miyaji
IPC分类号： H04J3/06 , H04J3/07
CPC分类号： H04J3/076
摘要： A pulse insertion circuit alternately distributes serial input data at a predetermined data clocking rate into first and second parallel input data, which are synchronously and simultaneously written into and read from a memory, the second input data as read being delayed by one bit. A selection means selects between the second input data and the one-bit delayed second input data and further switches between and establishes either a direct or a cross connection between the selected one of the second input data, as read or as delayed, and the first input data and the first and second output terminals thereof, at which there are produced, correspondingly, parallel and selected, first and second input data. A control means responds to a pulse insertion request to inhibit memory read-out by one read clock period and to control the switching means selectively to switch between the direct and cross-connections, the pulse addition being made to one of the parallel and selected, first and second input data, as specified by the pulse insertion request. Pulse insertion thus is performed at one-half the predetermined clocking rate, the selected and parallel, first and second input data with the required pulse inserted in the specified one thereof, thereafter being multiplexed and transmitted at the predetermined clocking rate.

9. 发明申请

US20120219291A1 CROSS-CONNECT SYSTEM AND CROSS-CONNECT METHOD 失效
标题翻译：交叉连接系统和交叉连接方法
公开(公告)号：US20120219291A1
公开(公告)日：2012-08-30
申请号：US13405530
申请日：2012-02-27
申请人： Isao Chiku , Yukio Suda , Shiuji Sakakura
发明人： Isao Chiku , Yukio Suda , Shiuji Sakakura
IPC分类号： H04J14/00
CPC分类号： H04J3/1652 , H04J3/0691 , H04J2203/0007 , H04J2203/0008
摘要： A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.
摘要翻译：交叉连接系统包括映射单元，其将与空间开关进行交叉连接的第二信号帧映射到与空间开关进行交叉连接的第三信号帧和时间开关; 选择单元，其选择与空间开关进行交叉连接的第一信号帧和时间切换以及对应的时钟信号，或者选择第三信号帧和对应的时钟信号; 交叉连接单元，其接收由选择单元选择的第一信号帧和相应的时钟信号或第三信号帧和对应的时钟信号，并对第一信号帧或第三信号帧执行交叉连接; 以及解映射单元，将从交叉连接单元输出的第三信号帧解映射成第二信号帧，并输出第二信号帧。

10. 发明授权

US08780897B2 Cross-connect system and cross-connect method 失效
标题翻译：交叉连接系统和交叉连接方式
公开(公告)号：US08780897B2
公开(公告)日：2014-07-15
申请号：US13405530
申请日：2012-02-27
申请人： Isao Chiku , Yukio Suda , Shiuji Sakakura
发明人： Isao Chiku , Yukio Suda , Shiuji Sakakura
IPC分类号： H04L12/50
CPC分类号： H04J3/1652 , H04J3/0691 , H04J2203/0007 , H04J2203/0008
摘要： A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.
摘要翻译：交叉连接系统包括映射单元，其将与空间开关进行交叉连接的第二信号帧映射到与空间开关进行交叉连接的第三信号帧和时间开关; 选择单元，其选择与空间开关进行交叉连接的第一信号帧和时间切换以及对应的时钟信号，或者选择第三信号帧和对应的时钟信号; 交叉连接单元，其接收由选择单元选择的第一信号帧和相应的时钟信号或第三信号帧和对应的时钟信号，并对第一信号帧或第三信号帧执行交叉连接; 以及解映射单元，将从交叉连接单元输出的第三信号帧解映射成第二信号帧，并输出第二信号帧。

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