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1. 发明申请

US20090179247A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090179247A1
公开(公告)日：2009-07-16
申请号：US12354254
申请日：2009-01-15
申请人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
发明人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L21/823892 , H01L27/092
摘要： A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.
摘要翻译：在具有三重阱结构的半导体器件中提供了可以提高制造成品率和产品可靠性的技术。形成在浅p型阱中的n沟道型场效应晶体管和形成在浅n型阱中的p沟道型场效应晶体管并且对电路操作无贡献的逆变器电路设置在在p型衬底中形成深n型阱; 使用第一层的布线将浅的p型阱连接到基板; 并且p沟道型场效应晶体管的栅电极和n沟道型场效应晶体管的栅电极使用最上层的布线连接到浅n型阱。

2. 发明授权

US08110878B2 Semiconductor device having a plurality of shallow wells 有权
标题翻译：具有多个浅井的半导体装置
公开(公告)号：US08110878B2
公开(公告)日：2012-02-07
申请号：US13179163
申请日：2011-07-08
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

3. 发明授权

US07982271B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07982271B2
公开(公告)日：2011-07-19
申请号：US12901858
申请日：2010-10-11
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

4. 发明授权

US07821076B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07821076B2
公开(公告)日：2010-10-26
申请号：US12422278
申请日：2009-04-12
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

5. 发明授权

US07714357B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07714357B2
公开(公告)日：2010-05-11
申请号：US12253850
申请日：2008-10-17
申请人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L29/74 , H01L23/52
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

6. 发明授权

US08482038B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08482038B2
公开(公告)日：2013-07-09
申请号：US13545553
申请日：2012-07-10
申请人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
发明人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
IPC分类号： H01L27/118
CPC分类号： H04B3/32
摘要： A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
摘要翻译：减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。这些导线布置成通过多个I / O单元并且彼此平行或多层。

7. 发明申请

US20110231694A1 DATA PROCESSING DEVICE AND MOBILE DEVICE 有权
标题翻译：数据处理设备和移动设备
公开(公告)号：US20110231694A1
公开(公告)日：2011-09-22
申请号：US13152676
申请日：2011-06-03
申请人： KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
发明人： KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
IPC分类号： G06F1/04
CPC分类号： G06F5/06 , G06F1/10
摘要： A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
摘要翻译：即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路，与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号存储卡。

8. 发明申请

US20090050940A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090050940A1
公开(公告)日：2009-02-26
申请号：US12253850
申请日：2008-10-17
申请人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L27/10
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

9. 发明授权

US08242541B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08242541B2
公开(公告)日：2012-08-14
申请号：US11651076
申请日：2007-01-09
申请人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
发明人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
IPC分类号： H01L27/118
CPC分类号： H04B3/32
摘要： A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
摘要翻译：减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。这些导线布置成通过多个I / O单元并且彼此平行或多层。

10. 发明申请

US20100171177A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100171177A1
公开(公告)日：2010-07-08
申请号：US12727811
申请日：2010-03-19
申请人： Takahiro HAYASHI , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro HAYASHI , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L27/06 , H01L23/58
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

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