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1. 发明申请

US20110063911A1 SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：US20110063911A1
公开(公告)日：2011-03-17
申请号：US12951616
申请日：2010-11-22
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

2. 发明授权

US08036038B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08036038B2
公开(公告)日：2011-10-11
申请号：US12951616
申请日：2010-11-22
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.
摘要翻译：半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度其他在字线方向。

3. 发明授权

US07859901B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07859901B2
公开(公告)日：2010-12-28
申请号：US12329007
申请日：2008-12-05
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.
摘要翻译：半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度其他在字线方向。

4. 发明申请

US20110310667A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20110310667A1
公开(公告)日：2011-12-22
申请号：US13219980
申请日：2011-08-29
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.
摘要翻译：半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度其他在字线方向。

5. 发明申请

US20090185423A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090185423A1
公开(公告)日：2009-07-23
申请号：US12329007
申请日：2008-12-05
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C16/04 , G11C8/00
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.
摘要翻译：半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度其他在字线方向。

6. 发明授权

US06512702B1 Non-volatile semiconductor memory device and data erase controlling method for use therein 失效
标题翻译：非挥发性半导体存储器件和数据擦除控制方法
公开(公告)号：US06512702B1
公开(公告)日：2003-01-28
申请号：US09539212
申请日：2000-03-30
申请人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
发明人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/344
摘要： A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.
摘要翻译：存储单元阵列被分成左和右单元阵列，每个阵列中的每一个包括多个块。基于结合到命令寄存器中的擦除命令标志和结合到地址寄存器中的地址，由擦除控制电路依次控制数据擦除。相对于右和左单元阵列的选定块执行批量擦除。在数据擦除之后，通过并行地相对于左和右单元阵列同时检索擦除块来执行关于擦除块的验证操作。因此，缩短在数据擦除之后检索用于验证操作的所选块所需的时间，从而缩短了执行整个数据擦除所需的时间。

7. 发明授权

US08223543B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08223543B2
公开(公告)日：2012-07-17
申请号：US13193968
申请日：2011-07-29
申请人： Makoto Iwai , Hiroshi Nakamura
发明人： Makoto Iwai , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/3436 , G11C16/3454
摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
摘要翻译：存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路，以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个当所选择的读取电位为第一值时。

8. 发明授权

US08009470B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08009470B2
公开(公告)日：2011-08-30
申请号：US12563296
申请日：2009-09-21
申请人： Makoto Iwai , Hiroshi Nakamura
发明人： Makoto Iwai , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/3436 , G11C16/3454
摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
摘要翻译：存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路，以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个当所选择的读取电位为第一值时。

9. 发明申请

US20100135078A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20100135078A1
公开(公告)日：2010-06-03
申请号：US12563296
申请日：2009-09-21
申请人： Makoto Iwai , Hiroshi Nakamura
发明人： Makoto Iwai , Hiroshi Nakamura
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/3436 , G11C16/3454
摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
摘要翻译：存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路，以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个当所选择的读取电位为第一值时。

10. 发明授权

US08477534B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08477534B2
公开(公告)日：2013-07-02
申请号：US13490541
申请日：2012-06-07
申请人： Makoto Iwai , Hiroshi Nakamura
发明人： Makoto Iwai , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/3436 , G11C16/3454
摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
摘要翻译：存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路，以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个当所选择的读取电位为第一值时。

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