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1. 发明授权

US4349743A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4349743A
公开(公告)日：1982-09-14
申请号：US206865
申请日：1980-11-14
申请人： Shinya Ohba , Shoji Hanamura , Toshifumi Ozaki , Masaharu Kubo , Masaaki Nakai , Kenji Takahashi , Masakazu Aoki , Iwao Takemoto , Haruhisa Ando , Ryuichi Izawa
发明人： Shinya Ohba , Shoji Hanamura , Toshifumi Ozaki , Masaharu Kubo , Masaaki Nakai , Kenji Takahashi , Masakazu Aoki , Iwao Takemoto , Haruhisa Ando , Ryuichi Izawa
IPC分类号： H01L27/14 , H01L27/146 , H04N3/14 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/365 , H04N5/372 , H04N5/374 , H04N5/378
CPC分类号： H01L27/14643 , H04N3/1512 , H04N3/1568
摘要： A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.
摘要翻译：一种固态成像装置，其中MOS传感器用于光电传感器部分，CTD移位寄存器用于读出电路，第一和第二传输门连接在垂直信号输出线和CTD之间，复位门连接在第一和第二传输门的接合点与复位电压线之间。采用在水平消隐期间将多行的信号输出传送到CTD的方法，并且在水平扫描期间同时读出多行的信号。在信号传输中，偏置电荷从CTD倾倒到垂直信号输出线路中，由偏置电荷和信号电荷组成的混合电荷转移到CTD。此后，读出信号。

2. 发明授权

US4392158A Interlaced solid-state imaging device 失效
标题翻译：隔行固态成像装置
公开(公告)号：US4392158A
公开(公告)日：1983-07-05
申请号：US257461
申请日：1981-04-24
申请人： Masakazu Aoki , Haruhisa Ando , Shinya Ohba , Shoji Hanamura , Iwao Takemoto , Ryuichi Izawa
发明人： Masakazu Aoki , Haruhisa Ando , Shinya Ohba , Shoji Hanamura , Iwao Takemoto , Ryuichi Izawa
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/359 , H04N5/374 , H04N3/14
CPC分类号： H04N3/1512 , H01L27/14643
摘要： In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.
摘要翻译：在具有在相同的半导体主体上二维排列的多个光电二极管的固态成像装置中，一组水平切换元件和一组拾取光电二极管的垂直开关元件，以及水平扫描电路和垂直扫描电路，其分别在水平和垂直开关元件上施加扫描脉冲，并且具有隔行扫描机构，其通过隔行扫描开关元件拾取多条垂直扫描线，以允许水平扫描多条扫描线的扫描线行一种固态成像装置，其特征在于，所述隔行扫描机构包括绝缘栅场效应晶体管，用于恢复由于交错开关元件而经历电压降的扫描脉冲的电压电平。

3. 发明授权

US4335406A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4335406A
公开(公告)日：1982-06-15
申请号：US163298
申请日：1980-06-26
申请人： Shinya Ohba , Masaharu Kubo , Iwao Takemoto , Shoji Hanamura , Masakazu Aoki
发明人： Shinya Ohba , Masaharu Kubo , Iwao Takemoto , Shoji Hanamura , Masakazu Aoki
IPC分类号： H01L27/146 , H04N5/335 , H04N5/365 , H04N5/374 , H04N3/15
CPC分类号： H04N5/2173
摘要： This invention provides a signal processing circuit of a solid-state imaging device utilizing discontinuous scanning pulses having fixed interval times, and with a fixed pattern noise-eliminating circuit of high performance. In the signal processing circuit of this invention, switching elements are disposed in a feedback circuit of a signal amplifier (for example, pre-amplifier) and at an output of the signal amplifier, whereby the fixed pattern noise is suppressed so as to attain a high signal-to-noise ratio.
摘要翻译：本发明提供一种使用具有固定间隔时间的不连续扫描脉冲的固态成像装置的信号处理电路，以及具有高性能的固定图案噪声消除电路。在本发明的信号处理电路中，开关元件设置在信号放大器（例如前置放大器）的反馈电路中，并在信号放大器的输出端设置，从而抑制固定图案噪声，从而达到高信噪比。

4. 发明授权

US4274113A Solid-state imaging device 失效
标题翻译：固态成像装置
公开(公告)号：US4274113A
公开(公告)日：1981-06-16
申请号：US118743
申请日：1980-02-05
申请人： Shinya Ohba , Shuhei Tanaka , Masaharu Kubo , Haruhisa Ando , Yataro Yamashita , Shoji Hanamura , Masakazu Aoki , Masaaki Nakai
发明人： Shinya Ohba , Shuhei Tanaka , Masaharu Kubo , Haruhisa Ando , Yataro Yamashita , Shoji Hanamura , Masakazu Aoki , Masaaki Nakai
IPC分类号： H04N5/217 , H04N5/335 , H04N5/365 , H04N5/374 , H04N5/378 , H04N3/12 , H04N3/14
CPC分类号： H04N5/2175 , H04N5/2173
摘要： A solid-state imaging device which is horizontally scanned by a discontinuous scanning pulse train, wherein an output signal of the device is integrated by a signal processing circuit which comprises an emitter follower (source follower) circuit and a capacitor disposed in parallel with the emitter follower (source follower) circuit, whereby noise components are canceled so as to derive only a video signal. With this solid-state imaging device, fixed pattern noise can be eliminated, and a good picture quality can be achieved.
摘要翻译：一种由不连续扫描脉冲串水平扫描的固态成像装置，其中该装置的输出信号由包括射极跟随器（源极跟随器）电路和与发射极并联设置的电容器的信号处理电路集成跟随器（源极跟随器）电路，由此噪声分量被消除以仅导出视频信号。利用该固态成像装置，可以消除固定图案噪声，并且可以实现良好的图像质量。

5. 发明授权

US5132771A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US5132771A
公开(公告)日：1992-07-21
申请号：US503928
申请日：1990-04-04
申请人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
发明人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.
摘要翻译：提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以彼此平行。

6. 发明授权

US5091325A Process for making MOS devices for low-temperature operation 失效
标题翻译：制造用于低温操作的MOS器件的方法
公开(公告)号：US5091325A
公开(公告)日：1992-02-25
申请号：US544045
申请日：1990-06-26
申请人： Shoji Hanamura , Masaaki Aoki , Toshiaki Masuhara
发明人： Shoji Hanamura , Masaaki Aoki , Toshiaki Masuhara
IPC分类号： G11C8/18 , H01L27/092 , H01L27/105 , H01L27/108 , H03K5/1534 , H03K19/00
CPC分类号： H03K5/1534 , G11C8/18 , H01L27/092 , H01L27/10805 , H03K19/0016 , H01L27/105
摘要： Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device). Such low impurity concentration layer is formed by evaporating amorphous silicon on a surface region of a semiconductor region of the device and passing the device through a low-temperature annealing process, the low impurity concentration layer having a lower total impurity concentration than that of the semiconductor region thereunder and having a thickness not more than 100 nm.

7. 发明授权

US5088065A Static type semiconductor memory 失效
标题翻译：静态型半导体存储器
公开(公告)号：US5088065A
公开(公告)日：1992-02-11
申请号：US593584
申请日：1990-10-05
申请人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
发明人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419
摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
摘要翻译：从静态半导体存储器的存储单元读出的信息在初级读出放大器，后级读出放大器和主放大器中进行多级感测放大，然后传输到输出缓冲电路的输入端。由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作，通过高速感测放大获得的输出信息输出不会消失。

8. 发明授权

US4841486A Semiconductor memory device and sense amplifier 失效
标题翻译：半导体存储器件和读出放大器
公开(公告)号：US4841486A
公开(公告)日：1989-06-20
申请号：US946776
申请日：1986-12-29
申请人： Osamu Minato , Toshiaki Masuhara , Koichiro Ishibashi , Shoji Hanamura , Shigeru Honjyo , Nobuyuki Moriwaki
发明人： Osamu Minato , Toshiaki Masuhara , Koichiro Ishibashi , Shoji Hanamura , Shigeru Honjyo , Nobuyuki Moriwaki
IPC分类号： H01L27/11 , G11C7/06 , G11C11/416 , G11C11/419 , H01L21/8244 , H01L27/10
CPC分类号： G11C11/419 , G11C7/062
摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.
摘要翻译：一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器在公共数据线上收集。读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为电压变化。每个MOS晶体管具有轻掺杂漏极结构。

9. 发明授权

US4768076A Recrystallized CMOS with different crystal planes 失效
标题翻译：具有不同晶面的重结晶CMOS
公开(公告)号：US4768076A
公开(公告)日：1988-08-30
申请号：US774705
申请日：1985-09-11
申请人： Masaaki Aoki , Toshiaki Masuhara , Terunori Warabisako , Shoji Hanamura , Yoshio Sakai , Seiichi Isomae , Satoshi Meguro , Shuji Ikeda
发明人： Masaaki Aoki , Toshiaki Masuhara , Terunori Warabisako , Shoji Hanamura , Yoshio Sakai , Seiichi Isomae , Satoshi Meguro , Shuji Ikeda
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L29/04 , H01L27/04
CPC分类号： H01L29/045 , H01L21/8221 , H01L27/0688 , H01L27/0922
摘要： A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.
摘要翻译：在具有平面方位（110）或（023）或靠近其的平面方位（与上述平面平行的方位角）的半导体晶体表面上形成CMOS IC，以便提高操作。在低温下，载流子迁移率对平面方位角的依赖性变得更显着，如图3所示。 1，并且根据平面放大移动性的差异。因此，当CMOS器件在低温（例如100°K或更低）下工作时，使用上述晶面有助于产生很大的效果，并且有助于高速操作器件。

10. 发明授权

US5126974A Sense amplifier for a memory device 失效
标题翻译：用于存储器件的感应放大器
公开(公告)号：US5126974A
公开(公告)日：1992-06-30
申请号：US465040
申请日：1990-01-16
申请人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
发明人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419 , G11C7/065
摘要： A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.
摘要翻译： MOS晶体管感测放大器采用交叉耦合的正反馈给差分放大器的负载电路，在放大器输出端具有均衡开关，优选也在输入端。该基本放大器电路可以分阶段地重复。当采用级时，期望第一级采用差分放大器的电流镜像负载来减少数据延迟。通过在读周期的感测部分期间通过在前置放大器上提供强放大来进一步降低数据延迟，当循环的感测部分完成时，前置放大器的放大减小，优选地被关闭，优选地，当输入和输出数据线独立于前置放大器直接连接，从而可以完全关闭前置放大器以降低功耗。

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