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1. 发明授权

US06326316B1 Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06326316B1
公开(公告)日：2001-12-04
申请号：US09562330
申请日：2000-05-01
申请人： Masahiro Kiyotoshi , Kazuhiro Eguchi
发明人： Masahiro Kiyotoshi , Kazuhiro Eguchi
IPC分类号： H01L2131
CPC分类号： H01L28/75 , H01L27/10852 , H01L28/55 , H01L28/91
摘要： Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.
摘要翻译：公开了一种半导体器件，包括半导体衬底，形成在半导体衬底中的单元晶体管，层间绝缘膜，其中形成有与单元晶体管的一部分连通的接触孔;埋入在所述接触孔中的接触孔层间电介质膜，由钽膜和形成在钽膜上的钌膜构成的钌/钽层叠膜形成的电容器下电极，下电极形成在层间绝缘膜上并连接到接触插塞，电容器在电容器下电极上形成的由金属氧化物构成的钌膜上形成的电介质膜和形成在电容器电介质膜上的电容器上电极，显示（00n）显着取向的钌膜，其中n表示正整数。

2. 发明授权

US6159868A Method of forming a high quality layer of BST 失效
标题翻译：形成BST高质量层的方法
公开(公告)号：US6159868A
公开(公告)日：2000-12-12
申请号：US239796
申请日：1999-01-29
申请人： Katsuhiko Hieda , Masahiro Kiyotoshi , Kazuhiro Eguchi
发明人： Katsuhiko Hieda , Masahiro Kiyotoshi , Kazuhiro Eguchi
IPC分类号： H01L21/8247 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/64
CPC分类号： H01L21/02197 , H01L21/022 , H01L21/02271 , H01L21/02356 , H01L21/31691
摘要： A method of manufacturing a semiconductor device characterized by a method of forming a thin insulating film mainly composed of barium strontium titanate, the method having a first step for forming, on a semiconductor substrate, a thin BST film by a CVD method, and a second step for performing annealing at a temperature higher than a temperature at the thin BST films is formed so that crystallinity of the thin BST films is improved, wherein the temperature of the semiconductor substrate is maintained at a temperature higher than 250.degree. C. in a period of time between the first step and the second step in order to prevent a deterioration in a quality of the thin BST film.
摘要翻译：一种制造半导体器件的方法，其特征在于，形成主要由钛酸钡锶组成的薄绝缘膜的方法，所述方法具有通过CVD方法在半导体衬底上形成薄BST膜的第一步骤，以及第二步骤形成在比BST薄的温度高的温度下进行退火的步骤，使得薄BST膜的结晶度提高，其中半导体衬底的温度在一段时间内保持在高于250℃的温度的时间在第一步骤和第二步骤之间，以防止薄BST薄膜的质量下降。

3. 发明授权

US6091099A Semiconductor device with tantalum and ruthenium 失效
标题翻译：具有钽和钌的半导体器件
公开(公告)号：US6091099A
公开(公告)日：2000-07-18
申请号：US969702
申请日：1997-11-13
申请人： Masahiro Kiyotoshi , Kazuhiro Eguchi
发明人： Masahiro Kiyotoshi , Kazuhiro Eguchi
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/92 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/75 , H01L27/10852 , H01L28/55 , H01L28/91
摘要： Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.
摘要翻译：公开了一种半导体器件，包括半导体衬底，形成在半导体衬底中的单元晶体管，层间绝缘膜，其中形成有与单元晶体管的一部分连通的接触孔;埋入在所述接触孔中的接触孔层间电介质膜，由钽膜和形成在钽膜上的钌膜构成的钌/钽层叠膜形成的电容器下电极，下电极形成在层间绝缘膜上并连接到接触插塞，电容器在电容器下电极上形成的由金属氧化物构成的钌膜上形成的电介质膜和形成在电容器电介质膜上的电容器上电极，显示（00n）显着取向的钌膜，其中n表示正整数。

4. 发明授权

US06495054B1 Etching method and cleaning method of chemical vapor growth apparatus 失效
公开(公告)号：US06495054B1
公开(公告)日：2002-12-17
申请号：US09429074
申请日：1999-10-29
申请人： Kazuhiro Eguchi , Katsuya Okumura , Masahiro Kiyotoshi , Katsuhiko Hieda , Soichi Yamazaki
发明人： Kazuhiro Eguchi , Katsuya Okumura , Masahiro Kiyotoshi , Katsuhiko Hieda , Soichi Yamazaki
IPC分类号： C03C1500
CPC分类号： C23C16/4405
摘要： Presented is an etching method capable of easily etching an oxide containing an alkaline-earth metal. One method is to etch the oxide by using an etching gas containing a halogen gas except for fluorine, an interhalogen compound consisting of only a halogen element except for fluorine, or a halogen hydride consisting of a halogen element except for fluorine and hydrogen. Particularly chlorides, bromides, and iodides of alkaline-earth metals have relatively high vapor pressures, so a thin film containing an alkaline-earth metal can be etched by using chlorine gas, bromine gas, or iodine gas. When a halogen gas containing fluorine is used, damages to SiO2 portions used in a film formation apparatus are prevented by coating these SiO2 portions with a fluoride of an alkaline-earth metal.

5. 发明授权

US06599794B2 Method of manufacturing a semiconductor device and semiconductor device 有权
公开(公告)号：US06599794B2
公开(公告)日：2003-07-29
申请号：US10195484
申请日：2002-07-16
申请人： Masahiro Kiyotoshi , Kazuhiro Eguchi , Masaaki Nakabayashi , Fumihiko Inoue
发明人： Masahiro Kiyotoshi , Kazuhiro Eguchi , Masaaki Nakabayashi , Fumihiko Inoue
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/11507 , H01L28/91
摘要： A method of manufacturing a semiconductor device comprising forming a sacrificial layer including one or more conductive film on a semiconductor substrate, forming a cavity used as a template of electroplating in the sacrificial layer, growing a metal film on a surface of the cavity by the electroplating using the conductive layer as a seed layer so that a cylindrical or convex electrode can be formed, and removing the sacrificial layer so that the electrode can be formed.

6. 发明授权

US5618761A Method of manufacturing a perovskite thin film dielectric 失效
标题翻译：钙钛矿薄膜电介质的制造方法
公开(公告)号：US5618761A
公开(公告)日：1997-04-08
申请号：US526387
申请日：1995-09-11
申请人： Kazuhiro Eguchi , Masahiro Kiyotoshi , Keitaro Imai
发明人： Kazuhiro Eguchi , Masahiro Kiyotoshi , Keitaro Imai
IPC分类号： H01L21/205 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10861 , H01L28/55
摘要： Disclosed is a method of manufacturing a semiconductor device, comprising the step of forming a dielectric thin film on a semiconductor layer, the dielectric thin film being made of a compound represented by the general formula (1) given below:ABO.sub.3 (1)where "A" is at least one element selected from the group consisting of Ca, Ba, Sr, Pb and La, and "B" is at least one element selected from the group consisting of Zr and Ti,The dielectric thin film being formed by a chemical vapor deposition under a pressure of 400 Torr or less and a temperature of 1,000.degree. C. or less by using a raw material gas containing a complex compound of element A with a .beta.-diketone, a complex compound of element B with a .beta.-diketone, and an oxidizing agent.
摘要翻译：公开了一种制造半导体器件的方法，包括在半导体层上形成电介质薄膜的步骤，所述电介质薄膜由以下给出的通式（1）表示的化合物制成：ABO3（1）其中“ A“是选自Ca，Ba，Sr，Pb和La中的至少一种元素，”B“是选自Zr和Ti中的至少一种元素。电介质薄膜由通过使用含有元素A的配位化合物与β-二酮的原料气体，元素B与β-二酮的络合物，在400Torr以下的压力和1000℃以下的温度下进行化学气相沉积，二酮和氧化剂。

7. 发明授权

US09087715B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09087715B2
公开(公告)日：2015-07-21
申请号：US13547645
申请日：2012-07-12
申请人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/115 , H01L27/088 , H01L21/265 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L27/24 , G11C16/04 , H01L29/66 , H01L29/68 , H01L29/788 , H01L29/792 , G11C16/10 , H01L29/82
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

8. 发明申请

US20130032873A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130032873A1
公开(公告)日：2013-02-07
申请号：US13326972
申请日：2011-12-15
申请人： Masahiro Kiyotoshi
发明人： Masahiro Kiyotoshi
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7926 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.
摘要翻译：根据一个实施例，半导体存储器件包括堆叠体，半导体柱和多个存储单元。层叠体包括设置在栅电极之间的多个层叠栅电极和电极间绝缘层。半导体柱穿过堆叠体。多个存储单元沿层叠方向设置。存储单元包括通过气隙设置在半导体柱和栅电极之间的电荷陷阱层。块绝缘层设置在电荷陷阱层和栅电极之间。多个存储单元中的每一个设置有被配置为保持电荷陷阱层和半导体柱之间的气隙距离的支撑部分。

9. 发明授权

US08143146B2 Method for manufacturing a nonvolatile storage device 有权
标题翻译：非易失性存储装置的制造方法
公开(公告)号：US08143146B2
公开(公告)日：2012-03-27
申请号：US12469872
申请日：2009-05-21
申请人： Masahiro Kiyotoshi
发明人： Masahiro Kiyotoshi
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1675
摘要： A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated.
摘要翻译：提供了一种制造具有堆叠在其中的多个单元存储层的非易失性存储装置的方法。每个单元存储层包括：沿第一方向延伸的第一互连; 沿第二方向延伸的第二互连; 记录单元，夹在第一和第二互连之间，并且能够响应于通过第一和第二互连提供的电流在第一状态和第二状态之间可逆地转换; 以及夹在所述第一布线和所述记录单元之间并且包括p型和n型杂质中的至少一种的整流元件。在该方法中，在多个单元存储层中使用的第一互连，第二互连，记录单元以及包含p型和n型杂质中的至少一种的非晶材料层形成在温度低于无定形材料基本上结晶的温度。在多个单元存储层中使用的非晶材料同时结晶化，并且包含在多个单元存储层中使用的非晶材料中的杂质同时被激活。

10. 发明授权

US08114755B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08114755B2
公开(公告)日：2012-02-14
申请号：US12146143
申请日：2008-06-25
申请人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
发明人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/764
摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

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