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1. 发明授权

US4860148A Semiconductor integrated circuit device with a protective circuit 失效
标题翻译：具有保护电路的半导体集成电路器件
公开(公告)号：US4860148A
公开(公告)日：1989-08-22
申请号：US37851
申请日：1987-04-13
申请人： Masahiro Iwamura , Ikuro Masuda , Hideaki Uchida
发明人： Masahiro Iwamura , Ikuro Masuda , Hideaki Uchida
IPC分类号： H03K17/00 , H01L21/822 , H01L27/02 , H01L27/04 , H03K17/08 , H03K19/003 , H03K19/01 , H03K19/0948
CPC分类号： H03K17/08 , H01L27/0248
摘要： A semiconductor integrated circuit device is provided with an input and/or an output terminal and at least one semiconductor device. The circuit has a resistor provided between the input terminal and/or the output terminal and one of the at least one semiconductor devices and an electronic switch connected in parallel with the resistor. The electronic switch is on-off controlled so as to exhibit a relatively low impedance when the semiconductor device is in operation and a relatively high impedance when the semiconductor device is not in operation. Thus, the semiconductor integrated circuit device is operable at a higher speed with an improved reliability and/or with controllable response characteristics, as compared with the conventional device.
摘要翻译：半导体集成电路器件设置有输入和/或输出端子和至少一个半导体器件。电路具有设置在输入端子和/或输出端子之间的电阻器，以及至少一个半导体器件中的一个和与电阻器并联连接的电子开关。当半导体器件处于工作状态时，电子开关被开关控制，以便表现出相对较低的阻抗，当半导体器件不工作时，电子开关具有较高的阻抗。因此，与常规器件相比，半导体集成电路器件可以以更高的速度操作，具有改善的可靠性和/或具有可控的响应特性。

2. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

3. 发明授权

US5153452A Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
标题翻译：具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC
公开(公告)号：US5153452A
公开(公告)日：1992-10-06
申请号：US401849
申请日：1989-08-30
申请人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/56 , H01L21/822 , H01L27/06
CPC分类号： G11C11/565 , G05F1/465 , G11C5/147 , G11C16/30
摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.
摘要翻译：提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

4. 发明授权

US4890017A CMOS-BiCMOS gate circuit 失效
标题翻译： CMOS-BiCMOS门电路
公开(公告)号：US4890017A
公开(公告)日：1989-12-26
申请号：US127184
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

5. 发明授权

US4719373A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4719373A
公开(公告)日：1988-01-12
申请号：US45216
申请日：1987-04-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/60 , H03K3/33
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

6. 发明授权

US5644548A Dynamic random access memory having bipolar and C-MOS transistor 失效
标题翻译：具有双极和C-MOS晶体管的动态随机存取存储器
公开(公告)号：US5644548A
公开(公告)日：1997-07-01
申请号：US703521
申请日：1996-08-27
申请人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
发明人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
IPC分类号： G11C11/408 , G11C11/4091 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4087 , G11C11/4082 , G11C11/4091 , G11C11/4096
摘要： A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.
摘要翻译：提供了一种动态随机存取存储器件，其具有动态存储器单元，耦合到动态存储单元的字线，耦合到动态存储单元的数据线，耦合到数据线的预充电电路，耦合到该字的字驱动器线和解码器耦合到字驱动器。耦合到解码器的多个地址线。解码器具有第一逻辑电路，其输入连接到多个地址线。解码器还具有一个锁存电路，其输入端连接到第一逻辑电路的输出，其输出端连接到字线。

7. 发明授权

US5239212A Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement 失效
标题翻译：具有改善放电布置的组合场效应和双极晶体管的栅极电路
公开(公告)号：US5239212A
公开(公告)日：1993-08-24
申请号：US986891
申请日：1992-12-08
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/01 , H01L27/0623 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于在场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

8. 发明授权

US4829201A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4829201A
公开(公告)日：1989-05-09
申请号：US127183
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

9. 发明授权

US4813020A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4813020A
公开(公告)日：1989-03-14
申请号：US170623
申请日：1988-03-17
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H01L27/088 , G11C7/10 , G11C8/08 , G11C11/418 , G11C19/28 , H01L21/8234 , H01L21/8236 , H01L21/8249 , H01L27/06 , H03K17/687 , H03K19/013 , H03K19/08 , H03K19/082 , H03K19/0944 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/418 , G11C19/28 , G11C7/1006 , G11C7/1051 , G11C8/08 , H03K19/0136 , H03K19/0826 , H03K19/09448 , G11C2207/108
摘要： A composite circuit including a MOS transistor and a bipolar transistor to be driven by the MOS transistors and forming an output stage, a logical inverter circuit connected to an output terminal of the composite circuit to invert the level of the output signal, and a MOS transistor having a source and a drain thereof parallelly connected across a collector and an emitter of the bipolar transistor are provided. When the bipolar transistor conducts with a voltage drop associated with a base-emitter voltage, the parallelly connected MOS transistor renders the bipolar transistor completely conductive so that a level-shiftless output signal is produced.
摘要翻译：一种复合电路，包括由MOS晶体管驱动并形成输出级的MOS晶体管和双极晶体管，连接到复合电路的输出端以反转输出信号电平的逻辑反相器电路和MOS晶体管具有并联连接在双极晶体管的集电极和发射极之间的源极和漏极。当双极晶体管以与基极 - 发射极电压相关联的电压降导通时，并联连接的MOS晶体管使双极晶体管完全导通，从而产生电平无移位输出信号。

10. 发明授权

US4694203A High speed bi-comos switching circuit 失效
标题翻译：高速双电源开关电路
公开(公告)号：US4694203A
公开(公告)日：1987-09-15
申请号：US716151
申请日：1985-03-26
申请人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
发明人： Akira Uragami , Yukio Suzuki , Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/08 , H03K17/04 , H03K17/0412 , H03K17/567 , H03K17/60 , H03K17/687 , H03K19/017 , H03K19/0944 , H03K19/013
CPC分类号： H03K17/04126 , H03K17/567 , H03K19/09448
摘要： A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.
摘要翻译：一种双极/ CMOS混合型开关电路，包括在输出级以图腾柱形式连接的两个npn型双极晶体管Q1，Q2，CMOS反相器和用于以互补方式驱动这些晶体管的NMOSFET M3;以及用于对存储在晶体管Q2的基极中的电荷进行放电的电阻装置R. 在不存在衬底效应的情况下，构成CMOS反相器的NMOSFET M2的阈值电压被设置为在没有衬底效应的情况下基本上等于NMOSFET M3的阈值电压，并且NMOSFET M3的沟道电导WN / LN 被设置为使得CMOS反相器的阈值电压VLT1和NMOSFET M3的实际阈值电压VLT2将几乎相同。由于上述结构，所以获得了允许很少的直流电流并且高速运行的开关电路。

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