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    • 5. 发明申请
    • IMAGE READING APPARATUS
    • 图像阅读器
    • US20110199655A1
    • 2011-08-18
    • US13029035
    • 2011-02-16
    • Masafumi Takahashi
    • Masafumi Takahashi
    • H04N1/04
    • H04N1/121H04N1/123H04N1/1235H04N1/193H04N2201/0081
    • A image reading apparatus includes a first conveyance unit which is configured to convey a document to a reading position of a platen while pinching the document, a second conveyance unit arranged on a downstream of the platen and configured to convey the document, an upstream rotary member arranged between the first conveyance unit and the second conveyance unit and configured to come into contact with the document at a position on an upstream of the reading position, and a downstream rotary member arranged between the first conveyance unit and the second conveyance unit and configured to come into contact with the document at a position on a downstream of the reading position, wherein a gap between the platen and the upstream rotary member is set smaller than a gap between the platen and the downstream rotary member.
    • 图像读取装置包括:第一输送单元,其被构造成在夹持原稿的同时将原稿输送到压纸盘的读取位置;第二输送单元,布置在压纸板的下游并构造成输送原稿;上游旋转构件 布置在所述第一输送单元和所述第二输送单元之间并构造成在所述读取位置的上游的位置处与所述原稿接触;以及下游旋转构件,布置在所述第一输送单元和所述第二输送单元之间, 在读取位置的下游位置处与文件接触,其中压板和上游旋转构件之间的间隙被设定为小于压板和下游旋转构件之间的间隙。
    • 6. 发明申请
    • WIRELESS RECEIVER
    • 无线接收器
    • US20080165862A1
    • 2008-07-10
    • US11775252
    • 2007-07-10
    • Masafumi Takahashi
    • Masafumi Takahashi
    • H04N7/24
    • H04L7/0337H04N21/2368H04N21/41407H04N21/4305H04N21/4341
    • A bitstream analysis circuit, generates a reference clock control data. A reference clock DPLL receives a system clock signal and reference clock control data from the analysis circuit and generates a reference clock signal. The reference clock DPLL comprises a 1/n frequency dividing circuit for frequency-dividing the system clock signal, and a 1/(n+1) frequency dividing circuit for frequency-dividing the system clock signal. A register stores data to set frequency dividing ratios of both frequency dividing circuits. A mixing ratio set register stores data to set a mixing ratio between output clock signals from both frequency dividing circuits and a mixing circuit, and mixes the output clock signals from both frequency dividing circuits at a mixing ratio in response to the data in the mixing ratio setting register.
    • 比特流分析电路,生成参考时钟控制数据。 参考时钟DPLL从分析电路接收系统时钟信号和参考时钟控制数据,并产生参考时钟信号。 参考时钟DPLL包括用于对系统时钟信号进行分频的1 / n分频电路和用于对系统时钟信号进行分频的1 /(n + 1)分频电路。 寄存器存储数据以设置两个分频电路的分频比。 混合比设定寄存器存储数据,以设定来自两个分频电路和混合电路的输出时钟信号之间的混合比,并且以混合比率混合来自两个分频电路的输出时钟信号,混合比率 设定寄存器。
    • 9. 发明授权
    • Microprocessor including memory for storing set value used to select and executive instruction after completing exception handling caused by exception request
    • 微处理器包括用于存储设置值的存储器,用于在完成由异常请求引起的异常处理之后选择和执行指令
    • US06757810B1
    • 2004-06-29
    • US09657906
    • 2000-09-08
    • Masafumi Takahashi
    • Masafumi Takahashi
    • G06F132
    • G06F9/30079G06F1/3203G06F1/3237G06F9/3861Y02D10/128
    • A control section sets a value “1” to a first flip-flop when a core executes a halt instruction. An OR circuit halts to output the clock. When the detection section detects an occurrence of the exception request, the control section copies the value “1” of the first flip-flop to a second flip-flop and then sets the value “0” to the first flip-flop to restart the supply of the clock to the core through the circuit. When detecting that the value “1” is set in the second flip-flop, the core judges that the state of the core was in the halt state when the exception request occurred, the core returns to the halt state after the completion of the exception handling by executing the halt instruction. When the second flip-flop does not store the value “1”, the core executes an instruction next to the address of the halt instruction.
    • 当核心执行停止指令时,控制部分向第一触发器设置值“1”。 OR电路停止输出时钟。 当检测部分检测到异常请求的发生时,控制部分将第一触发器的值“1”复制到第二触发器,然后将值“0”设置到第一触发器以重新开始 通过电路将时钟提供给核心。 当检测到第二个触发器中设置了值“1”时,核心在发生异常请求时判断核心的状态处于停止状态,核心在完成异常之后返回到停止状态 通过执行停止指令进行处理。 当第二触发器不存储值“1”时,核心执行停止指令的地址旁边的指令。