专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100083011A1 INFORMATION PROCESSING DEVICE 失效
标题翻译：信息处理设备
公开(公告)号：US20100083011A1
公开(公告)日：2010-04-01
申请号：US12466696
申请日：2009-05-15
申请人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
发明人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
IPC分类号： G06F15/76 , G06F1/10 , G06F1/26 , G06F9/02
CPC分类号： G06F1/3203 , G06F1/10 , Y02D10/126
摘要： In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.
摘要翻译：在具有例如六十四个处理器核心，片上存储器，与其连接的总线等的配置中，处理器核心由具有低电压的电源和具有低频率的时钟，总线由高电压电源和高频时钟驱动。每个处理器内核都配有一个总线接口和一个分频器，以便吸收总线与它们中的每一个之间的电源电压差和频率差。分频器从高频时钟产生低频时钟，总线接口提供电平转换功能，数据宽度转换功能，总线与总线接口之间的手抖功能等。

2. 发明申请

US20100117697A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION 失效
标题翻译：用于时钟信号同步的半导体集成电路和控制方法
公开(公告)号：US20100117697A1
公开(公告)日：2010-05-13
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

3. 发明授权

US08350595B2 Semiconductor integrated circuit and control method for clock signal synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US08350595B2
公开(公告)日：2013-01-08
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

4. 发明申请

US20120187993A1 Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US20120187993A1
公开(公告)日：2012-07-26
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

5. 发明授权

US08183899B2 Semiconductor integrated circuit and control method for clock signal synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US08183899B2
公开(公告)日：2012-05-22
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

6. 发明授权

US07443218B2 Semiconductor integrated circuit with pulsed clock data latch 有权
标题翻译：具有脉冲时钟数据锁存器的半导体集成电路
公开(公告)号：US07443218B2
公开(公告)日：2008-10-28
申请号：US11476040
申请日：2006-06-28
申请人： Masafumi Onouchi , Yusuke Kanno , Hiroyuki Mizuno , Yasuhisa Shimazaki , Tetsuya Yamada
发明人： Masafumi Onouchi , Yusuke Kanno , Hiroyuki Mizuno , Yasuhisa Shimazaki , Tetsuya Yamada
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/017 , H03K3/037
摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.
摘要翻译：可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。

7. 发明申请

US20070001734A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070001734A1
公开(公告)日：2007-01-04
申请号：US11476040
申请日：2006-06-28
申请人： Masafumi Onouchi , Yusuke Kanno , Hiroyuki Mizuno , Yasuhisa Shimazaki , Tetsuya Yamada
发明人： Masafumi Onouchi , Yusuke Kanno , Hiroyuki Mizuno , Yasuhisa Shimazaki , Tetsuya Yamada
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/017 , H03K3/037
摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.
摘要翻译：可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。

8. 发明授权

US07899643B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07899643B2
公开(公告)日：2011-03-01
申请号：US11935790
申请日：2007-11-06
申请人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
发明人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
IPC分类号： G01K1/12 , G06F19/00
CPC分类号： G06F1/3228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

9. 发明申请

US20080114967A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080114967A1
公开(公告)日：2008-05-15
申请号：US11935790
申请日：2007-11-06
申请人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
发明人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
IPC分类号： G06F9/302
CPC分类号： G06F1/3228 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

10. 发明授权

US08829968B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08829968B2
公开(公告)日：2014-09-09
申请号：US12555143
申请日：2009-09-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式