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1. 发明授权

US06516454B1 Method of estimating time delay 有权
标题翻译：估计时间延迟的方法
公开(公告)号：US06516454B1
公开(公告)日：2003-02-04
申请号：US09714101
申请日：2000-11-17
申请人： Masaaki Hirata , Ryuichi Yamaguchi
发明人： Masaaki Hirata , Ryuichi Yamaguchi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of accurately estimating a time delay caused by a target cell where a target supply voltage is applied to the cell. Time delays, caused by a representative cell, are represented as a function of supply voltages applied to the cell, thereby deriving an approximation function k1. An interpolation function k2 is derived from the approximation function k1 by reference to two points P1 and P2. P1 indicates a time delay T1 caused by the target cell where a supply voltage V1 is applied thereto, while P2 indicates a time delay T2 caused by the target cell where a different supply voltage V2 is applied thereto. Thus, the interpolation function k2 represents the time delays caused by the target cell as a function of supply voltages. And by using this interpolation function k2, a time delay caused by the target cell at the target supply voltage can be estimated accurately.
摘要翻译：一种精确地估计由目标电池施加到电池的目标电池引起的时间延迟的方法。由代表性单元导致的时间延迟被表示为施加到单元的电源电压的函数，从而导出近似函数k1。通过参照两点P1和P2从近似函数k1导出插值函数k2。 P1表示由施加电源电压V1的目标单元引起的时间延迟T1，而P2表示由施加不同电源电压V2的目标单元引起的时间延迟T2。因此，内插函数k2表示作为电源电压的函数的由目标单元引起的时间延迟。并且通过使用该内插函数k2，可以准确地估计目标电池在目标电源电压下引起的时间延迟。

2. 发明授权

US07925998B2 Delay calculating method in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的延迟计算方法
公开(公告)号：US07925998B2
公开(公告)日：2011-04-12
申请号：US11296640
申请日：2005-12-08
申请人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
摘要翻译：在功能表达式中预先获得单元的输入引脚电容，并且以这样的方式计算延迟，使得在每种情况下以输入转换和驱动负载电容的功能计算输入引脚电容。在单元特征处理中，获得在输入端子的电压值达到基准电压之前进入输入端子的电流的总体积，从而可以获得接近实际输入引脚电容的值。

3. 发明申请

US20070300196A1 Delay calculating method in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的延迟计算方法
公开(公告)号：US20070300196A1
公开(公告)日：2007-12-27
申请号：US11296640
申请日：2005-12-08
申请人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
摘要翻译：在功能表达式中预先获得单元的输入引脚电容，并且以这样的方式计算延迟，使得在每种情况下以输入转换和驱动负载电容的功能计算输入引脚电容。在单元特征处理中，获得在输入端子的电压值达到基准电压之前进入输入端子的电流的总体积，从而可以获得接近实际输入引脚电容的值。

4. 发明授权

US07225418B2 Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same 有权
标题翻译：半导体集成电路器件的运行分析方法，使用的分析系统及其优化设计方法
公开(公告)号：US07225418B2
公开(公告)日：2007-05-29
申请号：US10863231
申请日：2004-06-09
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/31928
摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.
摘要翻译：包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息：抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。

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