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1. 发明授权

US06516454B1 Method of estimating time delay 有权
标题翻译：估计时间延迟的方法
公开(公告)号：US06516454B1
公开(公告)日：2003-02-04
申请号：US09714101
申请日：2000-11-17
申请人： Masaaki Hirata , Ryuichi Yamaguchi
发明人： Masaaki Hirata , Ryuichi Yamaguchi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of accurately estimating a time delay caused by a target cell where a target supply voltage is applied to the cell. Time delays, caused by a representative cell, are represented as a function of supply voltages applied to the cell, thereby deriving an approximation function k1. An interpolation function k2 is derived from the approximation function k1 by reference to two points P1 and P2. P1 indicates a time delay T1 caused by the target cell where a supply voltage V1 is applied thereto, while P2 indicates a time delay T2 caused by the target cell where a different supply voltage V2 is applied thereto. Thus, the interpolation function k2 represents the time delays caused by the target cell as a function of supply voltages. And by using this interpolation function k2, a time delay caused by the target cell at the target supply voltage can be estimated accurately.
摘要翻译：一种精确地估计由目标电池施加到电池的目标电池引起的时间延迟的方法。由代表性单元导致的时间延迟被表示为施加到单元的电源电压的函数，从而导出近似函数k1。通过参照两点P1和P2从近似函数k1导出插值函数k2。 P1表示由施加电源电压V1的目标单元引起的时间延迟T1，而P2表示由施加不同电源电压V2的目标单元引起的时间延迟T2。因此，内插函数k2表示作为电源电压的函数的由目标单元引起的时间延迟。并且通过使用该内插函数k2，可以准确地估计目标电池在目标电源电压下引起的时间延迟。

2. 发明授权

US06292928B1 Line path determining method and delay estimating method 失效
标题翻译：线路确定方法和延迟估计方法
公开(公告)号：US06292928B1
公开(公告)日：2001-09-18
申请号：US09227858
申请日：1999-01-11
申请人： Ryuichi Yamaguchi , Keiichi Kurokawa
发明人： Ryuichi Yamaguchi , Keiichi Kurokawa
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/5022
摘要： A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.
摘要翻译：考虑到粗略路由中的相邻线路的影响来估计线路电容，从而可以确定线路路径以便不存在定时误差。从目标集成电路生成路由图，并且基于针对路由图的每个边缘设置的通过成本来初始确定单元到单元线的线路径。对于路由图的每个边缘，获得通过边缘的单元到单元线的数量作为线密度，并且考虑到相邻线的影响的每条线路的线电容被估计为线密度的基础。验证是否存在估计延迟时间的定时误差，并且当集成电路不满足预定的定时约束时，线路径被重新确定，其中每个边缘的通过成本被允许受到线电容。或者，对互连层的分配改变或者线间距离增加，使得集成电路可以满足时序约束。

3. 发明授权

US5894421A Method and apparatus for calculating slew rates and signal propagation times for signal waveforms 失效
标题翻译：用于计算信号波形的转换速率和信号传播时间的方法和装置
公开(公告)号：US5894421A
公开(公告)日：1999-04-13
申请号：US612330
申请日：1996-03-07
申请人： Ryuichi Yamaguchi , Yasuhiro Tomita
发明人： Ryuichi Yamaguchi , Yasuhiro Tomita
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A signal propagation time in an integrated circuit can be calculated based on a signal delay time in each of the cells composing the integrated circuit. The signal delay time in each cell can be calculated from the load capacity of a wire connected to an output terminal of the cell and from the slew of the waveform of an input signal. To calculate the slew of the waveform of the input signal, it is required to trace back the path of the input signal. When a feedback loop exists in the integrated circuit, the process of tracing back the path of the input signal may result in an endless loop. To prevent the occurrence of the endless loop, if an input terminal for a clock signal is present in a cell having an output terminal at which a signal waveform is not calculated, the signal waveform at the output terminal is calculated based on the waveform of the clock signal. In addition, a directory in which the correspondence of the output terminal and the input terminal is recorded is produced so that the signal waveform at the output terminal can be calculated based on the signal waveform at the corresponding input terminal recorded in the directory.
摘要翻译：可以基于构成集成电路的每个单元中的信号延迟时间来计算集成电路中的信号传播时间。每个单元中的信号延迟时间可以从连接到单元的输出端的导线的负载容量和输入信号的波形的斜率来计算。为了计算输入信号波形的斜率，需要追溯输入信号的路径。当集成电路中存在反馈回路时，跟踪输入信号路径的过程可能导致无限循环。为了防止无限循环的发生，如果在具有不计算信号波形的输出端子的单元中存在用于时钟信号的输入端子，则基于输出端子的波形来计算输出端子处的信号波形时钟信号。此外，产生记录输出端子和输入端子的对应关系的目录，使得可以基于记录在目录中的相应输入端子处的信号波形来计算输出端子处的信号波形。

4. 发明授权

US5047949A Standard cell LSI layout method 失效
标题翻译：标准单元LSI布局方法
公开(公告)号：US5047949A
公开(公告)日：1991-09-10
申请号：US534358
申请日：1990-06-06
申请人： Ryuichi Yamaguchi , Atsushi Yamamoto
发明人： Ryuichi Yamaguchi , Atsushi Yamamoto
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/118
CPC分类号： H01L27/118 , G06F17/5068 , H01L27/0207
摘要： In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.
摘要翻译：在包括通过放置由标准单元组选择的标准单元组成的单元行组和通过布线标准单元而形成的功能电路的标准单元LSI中，包括以下步骤的标准单元LSI布局方法：比较布线中的布线密度通过在更拥挤的路由区域中沿着更分散的路由区域的方向移动一个或多个标准小区，位于单元行之间并弯曲单元行的区域。单元行在包围单元行的路由区域的每个高拥塞区域之间的点处被弯曲，这取决于路由密度。可以提供链接单元，用于连接已经移位的标准单元的电源和接地引脚，并构成弯曲的单元行。链接单元可以通过将标准单元存储在库中并且在定义标准单元LSI布局时参考库中的标准单元来存储在构成单元行的系统中的库中。

5. 发明授权

US06507936B2 Timing verifying method 有权
标题翻译：定时验证方法
公开(公告)号：US06507936B2
公开(公告)日：2003-01-14
申请号：US09838179
申请日：2001-04-20
申请人： Ryuichi Yamaguchi
发明人： Ryuichi Yamaguchi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.
摘要翻译：根据本发明的定时验证方法，独立于执行逻辑模拟的步骤，执行考虑到处理变化条件来计算由线延迟时间和单元延迟时间组成的变化延迟时间的步骤半导体集成电路基于计算出的变化延迟时间。

6. 发明授权

US5598217A Circuit for executing an interpolation processing on a sub-sampled image signal 失效
标题翻译：用于对子采样图像信号执行插值处理的电路
公开(公告)号：US5598217A
公开(公告)日：1997-01-28
申请号：US347115
申请日：1994-11-23
申请人： Ryuichi Yamaguchi
发明人： Ryuichi Yamaguchi
IPC分类号： H04N7/26 , H04N7/46 , H04N7/24
CPC分类号： H04N19/59 , H04N19/63 , H04N19/80
摘要： After limited in band area with a vertical or horizontal low-pass filter in a sub-sampling circuit at the image-signal transmitting side, an image signal is sub-sampled as inter-frame offset in the form of a quincunx, and then transmitted to an image-signal receiving side through a transmission system. The sampling rate of the image signal thus received is converted by a sampling rate conversion portion. According to the operation of a changeover switch by the operator who watches a Braun tube for image reproduction, a selector selects the image signal interpolated with a vertical filter of a low-pass portion when the sub-sampling circuit uses a vertical filter, or the image signal interpolated with both vertical and horizontal low-pass filters when the sub-sampling circuit uses a two dimensional filter. Thus, there is supplied an image signal which has been interpolated with a low-pass filter of which transmissible band area is identical with or approximate to that of the low-pass filter in the sub-sampling circuit at the signal transmitting side, such that the image signal contains no aliasing interference of a spatial frequency band area. Thus, there can be reproduced a good picture in which a horizontal straight line is not displayed as a broken line.
摘要翻译：在图像信号发送侧的子采样电路中，在带有垂直或水平低通滤波器的频带区域有限之后，将图像信号作为帧间偏移进行子采样，以五点形式发送，然后发送通过传输系统到图像信号接收侧。如此接收的图像信号的采样率由采样率转换部分转换。根据操作人员观察用于图像再现的布劳恩管的切换开关的操作，当副采样电路使用垂直滤波器时，选择器选择用低通部分的垂直滤波器内插的图像信号，或者当子采样电路使用二维滤波器时，利用垂直和水平低通滤波器内插的图像信号。因此，在信号发送侧的副采样电路中，利用低通滤波器对传输带区域与低通滤波器相同或接近的低通滤波器进行了内插的图像信号，使得图像信号不包含空间频带区域的混叠干扰。因此，可以再现没有以虚线显示水平直线的良好图像。

7. 发明授权

US5568635A Physical memory allocation system, program execution scheduling system, and information processor 失效
标题翻译：物理内存分配系统，程序执行调度系统和信息处理器
公开(公告)号：US5568635A
公开(公告)日：1996-10-22
申请号：US200489
申请日：1994-02-23
申请人： Ryuichi Yamaguchi
发明人： Ryuichi Yamaguchi
IPC分类号： G06F12/10 , G06F9/46 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0223 , G06F12/08
摘要： A physical memory allocation system comprising an area estimation section, a program modification section, a program size read-in section, a memory size read-in section, a user control table, a size compare section, and an area allocation section. The area estimation section, after a program has been run for a predetermined period of time, measures a memory area size referred to by the program (i.e. the program size). The program modification section writes the program size to the program. The program size read-in section inputs the program size and the memory size read-in section inputs a user allocation size held at the user control table at program execution time. The size compare section makes a comparison in size between the user allocation size and the program size thereby outputting one of these two sizes that is found to be smaller than the other as an at-execution-time size. In the area allocation section, an amount of physical memory that a program can use is taken as an at-execution-time size. Taking such a physical memory size as a low limit, physical memory allocation is carried out effectively. This reduces the frequency of swapping and the loss of time.
摘要翻译：一种物理存储器分配系统，包括区域估计部分，程序修改部分，程序大小读入部分，存储器大小读入部分，用户控制表，大小比较部分和区域分配部分。区域估计部分在程序已经运行预定时间段之后，测量由程序引用的存储器区域大小（即，程序大小）。程序修改部分将程序大小写入程序。程序大小读入部分输入程序大小，并且存储器大小读入部分在程序执行时间输入用户控制表中保存的用户分配大小。大小比较部分在用户分配大小和程序大小之间进行大小比较，从而将发现比另一个小的这两个尺寸之一作为执行时间大小输出。在区域分配部分中，将程序可以使用的物理存储器的量作为执行时间大小。将这样的物理内存大小作为下限，可以有效地进行物理内存分配。这减少了交换的频率和时间的损失。

8. 发明授权

US5761081A Method of evaluating signal propagation delay in logic integrated circuit 失效
标题翻译：评估逻辑集成电路中信号传播延迟的方法
公开(公告)号：US5761081A
公开(公告)日：1998-06-02
申请号：US638079
申请日：1996-04-26
申请人： Yasuhiro Tomita , Nobufusa Iwanishi , Ryuichi Yamaguchi , Hisakazu Edamatsu
发明人： Yasuhiro Tomita , Nobufusa Iwanishi , Ryuichi Yamaguchi , Hisakazu Edamatsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.
摘要翻译：评估具有第一反相器单元和通过单元间线连接的第二反相器单元的逆变器链中的信号传播延迟。为了确保总是将第一反相器单元延迟评估为正（A），将第一反相器单元的输入引脚电压的增加的逻辑阈值电压设置为低于第一反相器单元的开关阈值电压的电压和（B）将第一反相器单元的输入引脚电压降低的逻辑阈值电压设定为高于第一反相器单元的开关阈值电压的电压。类似地，确定用于第二逆变器单元的输入引脚电压的增加和减小的逻辑阈值电压。此外，为了保证细胞间线延迟始终被评估为正，使得第一反相器单元的输出引脚电压的逻辑阈值电压与第二反相器单元的输入引脚电压的逻辑阈值电压一致。

9. 发明授权

US5468894A Method of manufacturing FSi(OR).sub.3 失效
标题翻译：制造FSi（OR）的方法3
公开(公告)号：US5468894A
公开(公告)日：1995-11-21
申请号：US215568
申请日：1994-03-22
申请人： Ryuichi Yamaguchi , Koichi Kiso , Kiyoshi Tazuke , Hideaki Machida , Katsuhiro Mihirogi , Yukichi Takamatsu
发明人： Ryuichi Yamaguchi , Koichi Kiso , Kiyoshi Tazuke , Hideaki Machida , Katsuhiro Mihirogi , Yukichi Takamatsu
IPC分类号： C07F7/02 , C07F7/08
CPC分类号： C07F7/025
摘要： By reacting Si(OR).sub.4 with HF, FSi (OR).sub.3 of high purity can be obtained easily and economically.
摘要翻译：通过使Si（OR）4与HF反应，可以容易且经济地获得高纯度的FSi（OR）3。

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