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1. 发明授权

US06492229B2 Semiconductor device having reduced field oxide recess and method of fabrication 失效
标题翻译：具有减小的场氧化物凹陷的半导体器件和制造方法
公开(公告)号：US06492229B2
公开(公告)日：2002-12-10
申请号：US09729516
申请日：2000-12-04
申请人： Masaaki Higashitani , Toru Ishigaki , Hao Fang
发明人： Masaaki Higashitani , Toru Ishigaki , Hao Fang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.
摘要翻译：公开了一种具有减小的场氧化物凹陷和制造方法的半导体器件。制造半导体器件的方法是通过在场氧化之后对衬底进行HF浸渍法，然后进行选择栅极氧化而开始的。此后，进行核心植入和场植入。在植入物之后，沉积隧道氧化物掩模。然后在不被隧道氧化物掩模覆盖的区域中蚀刻选择栅极氧化物，并且执行隧道氧化。

2. 发明申请

US20080144384A1 METHODS FOR ACTIVE BOOSTING TO MINIMIZE CAPACITIVE COUPLING EFFECT BETWEEN ADJACENT GATES OF FLASH MEMORY DEVICES 有权
标题翻译：用于主动加速以最小化闪存存储器件相邻栅极之间的电容耦合效应的方法
公开(公告)号：US20080144384A1
公开(公告)日：2008-06-19
申请号：US12031640
申请日：2008-02-14
申请人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
发明人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

3. 发明授权

US06448593B1 Type-1 polysilicon electrostatic discharge transistors 失效
标题翻译： 1型多晶硅静电放电晶体管
公开(公告)号：US06448593B1
公开(公告)日：2002-09-10
申请号：US09491532
申请日：2000-01-26
申请人： Masaaki Higashitani , Hao Fang
发明人： Masaaki Higashitani , Hao Fang
IPC分类号： H01L2902
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/0266
摘要： The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.
摘要翻译：本发明提供一种用于在闪存芯片中提供多晶硅型1型ESD晶体管的方法和装置。该方法和装置包括提供包括栅极，浮动栅极，中等掺杂结以及源极和漏极的选择栅极晶体管。所述方法和装置还包括通过执行轻掺杂漏极（LDD）掩模和蚀刻，执行LDD间隔物沉积和LDD间隔物蚀刻以及执行N +注入掩模和N +注入来形成源极和漏极。

4. 发明授权

US06312991B1 Elimination of poly cap easy poly 1 contact for NAND product 有权
标题翻译：消除聚碳酸酯容易聚1接触的NAND产品
公开(公告)号：US06312991B1
公开(公告)日：2001-11-06
申请号：US09531582
申请日：2000-03-21
申请人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
发明人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.
摘要翻译：形成NAND型快闪存储器件的方法（200）包括以下步骤：在衬底（102）上形成氧化物层（202），并在氧化物层上形成第一导电层（106）。蚀刻第一导电层（106）以在存储单元区域（111）中的选择栅极晶体管区域（105）和浮动栅极结构（106a，106b）中形成栅极结构（107）。然后在存储单元区域（111）之上形成第一绝缘层（110），并且在第一绝缘层（110）之上形成第二导电层（112,118）。在存储单元区域（111）中对字线（122）进行构图以形成控制栅极区域，并且在邻近字线的区域（102,132）中形成在衬底（102）中的源极和漏极区域（130,132） 122）并且在与栅极结构（107）相邻的区域中。在选择栅极晶体管区域（105）和存储单元区域（111）上形成第二绝缘层（140），并且在第二绝缘层（140）中形成第一和第二接触开口至栅极结构（107））和控制栅极区域，其中通过第二绝缘层（140）到达栅极结构（107）并且向下到控制栅极区域的深度（X）大致相同，从而消除了栅极结构的实质上的过蚀刻接触开口

5. 发明授权

US07436703B2 Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 有权
标题翻译：主动升压以最小化闪存器件的相邻门之间的电容耦合效应
公开(公告)号：US07436703B2
公开(公告)日：2008-10-14
申请号：US11319908
申请日：2005-12-27
申请人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
发明人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

6. 发明授权

US07362615B2 Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 有权
标题翻译：用于主动升压以最小化闪存器件的相邻栅极之间的电容耦合效应的方法
公开(公告)号：US07362615B2
公开(公告)日：2008-04-22
申请号：US11319260
申请日：2005-12-27
申请人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
发明人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

7. 发明申请

US20070147119A1 Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 有权
标题翻译：主动升压以最小化闪存器件的相邻门之间的电容耦合效应
公开(公告)号：US20070147119A1
公开(公告)日：2007-06-28
申请号：US11319908
申请日：2005-12-27
申请人： Tuan Pham , Masaaki Higashitani , Hao Fang , Gerrit Hemink
发明人： Tuan Pham , Masaaki Higashitani , Hao Fang , Gerrit Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

8. 发明授权

US06448609B1 Method and system for providing a polysilicon stringer monitor 失效
标题翻译：提供多晶硅纵梁监视器的方法和系统
公开(公告)号：US06448609B1
公开(公告)日：2002-09-10
申请号：US09429244
申请日：1999-10-28
申请人： Masaaki Higashitani , Hao Fang
发明人： Masaaki Higashitani , Hao Fang
IPC分类号： H01L29792
CPC分类号： H01L22/34
摘要： A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.
摘要翻译：一种使用多晶硅纵梁监测器在存储器阵列上检测多晶硅桁条存在的系统和方法。多晶硅纵梁监视器包括连续的2层多晶硅，跨越有源区形成第一行和第二行，并覆盖第一行和第二行之间的有源区。多晶硅纵梁监视器还包括在第一行下方延伸的连续的1层多晶硅，其中第一层也覆盖第一行和第二行之间的有效区域，并且覆盖第二行下方的有效区域。

9. 发明授权

US06346737B1 Shallow trench isolation process particularly suited for high voltage circuits 失效
标题翻译：浅沟槽隔离工艺特别适用于高压电路
公开(公告)号：US06346737B1
公开(公告)日：2002-02-12
申请号：US09109755
申请日：1998-07-02
申请人： Masaaki Higashitani , Hao Fang
发明人： Masaaki Higashitani , Hao Fang
IPC分类号： H01L2900
CPC分类号： H01L21/76235 , H01L21/76202 , H01L21/76224
摘要： A process which includes forming trench structures (28) in a substrate (12) as part of both the STI isolation structure and the LOCOS/STI isolation structure. Thereafter, a field oxide (34a) is formed which simultaneously forms a portion of the STI isolation structure and a portion of the LOCOS/STI isolation structure. Consequently, three different isolation structures may be formed without requiring a substantial increase in the complexity or number of processing steps.
摘要翻译：包括在衬底（12）中形成作为STI隔离结构和LOCOS / STI隔离结构两者的一部分的沟槽结构（28）的工艺。此后，形成场同时形成STI隔离结构的一部分和LOCOS / STI隔离结构的一部分的场氧化物（34a）。因此，可以形成三个不同的隔离结构，而不需要大大增加处理步骤的复杂性或数量。

10. 发明授权

US6159795A Low voltage junction and high voltage junction optimization for flash memory 失效
标题翻译：闪存的低电压结和高压结优化
公开(公告)号：US6159795A
公开(公告)日：2000-12-12
申请号：US109664
申请日：1998-07-02
申请人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
发明人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/976
摘要： An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
摘要翻译：执行中间植入步骤以优化浮动型存储器集成电路的周边部分中的晶体管的性能。在相应的浮动栅型存储器件中形成浮置栅极的多晶硅层（Poly 1）防止优化注入穿透到形成浮栅存储器件的芯区域中。这允许在不需要附加掩模的情况下执行优化植入，从而降低成本和生产时间。

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