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1. 发明授权

US08951859B2 Method for fabricating passive devices for 3D non-volatile memory 有权
标题翻译：用于制造3D非易失性存储器的无源器件的方法
公开(公告)号：US08951859B2
公开(公告)日：2015-02-10
申请号：US13301560
申请日：2011-11-21
申请人： Masaaki Higashitani , Peter Rabkin
发明人： Masaaki Higashitani , Peter Rabkin
IPC分类号： H01L21/8239 , H01L29/792 , H01L49/02 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L28/20 , H01L28/87 , H01L28/88
摘要： A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
摘要翻译：一种用于制造用于3D非易失性存储器件的诸如电阻器和电容器的无源器件的方法。在衬底的外围区域中，叠层中提供诸如氧化物和诸如重掺杂多晶硅或金属硅化物的导电材料的电介质的交替层。衬底包括连接到电路的一个或多个下部金属层。在堆叠上方形成一个或多个上金属层。形成了从导电材料层延伸到一个或多个上金属层的部分的接触结构，使得导电材料层彼此平行或连续地由接触结构和至少一个上金属层。附加接触结构可以将电路连接到一个或多个上金属层。可以使用常规的处理步骤与3D存储器阵列同时地制造无源器件。

2. 发明授权

US08933502B2 3D non-volatile memory with metal silicide interconnect 有权
标题翻译：具有金属硅化物互连的3D非易失性存储器
公开(公告)号：US08933502B2
公开(公告)日：2015-01-13
申请号：US13301597
申请日：2011-11-21
申请人： Masaaki Higashitani , Peter Rabkin
发明人： Masaaki Higashitani , Peter Rabkin
IPC分类号： H01L27/06 , G11C16/06 , H01L27/115 , G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L23/53209 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
摘要翻译：堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域，以及例如阵列中途并且延伸阵列的长度的互连区域。互连区域包括在绝缘填充的狭缝之间延伸的至少一个金属硅化物互连，并且不包括NAND单元的垂直列。金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。金属硅化物互连也可以形成在衬底的周边区域中。接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

3. 发明申请

US20130314995A1 Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory 审中-公开
标题翻译：在非易失性存储器中擦除期间控制虚拟字线偏置
公开(公告)号：US20130314995A1
公开(公告)日：2013-11-28
申请号：US13479649
申请日：2012-05-24
申请人： Deepanshu Dutta , Mohan Dunga , Masaaki Higashitani
发明人： Deepanshu Dutta , Mohan Dunga , Masaaki Higashitani
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.
摘要翻译：一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。选择栅极晶体管的电压也可以电容耦合得更高。衬底电压可以逐步增加和/或作为连续斜坡增加。在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。在另一种方法中，外部和内部虚拟存储元件都浮起来。由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

4. 发明授权

US08450174B2 Non-volatile storage having a connected source and well 有权
标题翻译：具有连接源的良好的非易失性存储器
公开(公告)号：US08450174B2
公开(公告)日：2013-05-28
申请号：US13173537
申请日：2011-06-30
申请人： Masaaki Higashitani
发明人： Masaaki Higashitani
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/743 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.
摘要翻译：公开了一种非易失性存储装置，其包括形成在阱上的一组连接的非易失性存储元件，位于阱中的位线触点，位于阱中的源极线接触件，连接到该阱的位线位线接触，以及连接到源极线接触点和阱的源极线。

5. 发明申请

US20130130468A1 Method For Fabricating Passive Devices For 3D Non-Volatile Memory 有权
标题翻译：用于制造3D非易失性存储器的无源器件的方法
公开(公告)号：US20130130468A1
公开(公告)日：2013-05-23
申请号：US13301560
申请日：2011-11-21
申请人： Masaaki Higashitani , Peter Rabkin
发明人： Masaaki Higashitani , Peter Rabkin
IPC分类号： H01L21/02
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L28/20 , H01L28/87 , H01L28/88
摘要： A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
摘要翻译：一种用于制造用于3D非易失性存储器件的诸如电阻器和电容器的无源器件的方法。在衬底的外围区域中，叠层中提供诸如氧化物和诸如重掺杂多晶硅或金属硅化物的导电材料的电介质的交替层。衬底包括连接到电路的一个或多个下部金属层。在堆叠上方形成一个或多个上金属层。形成了从导电材料层延伸到一个或多个上金属层的部分的接触结构，使得导电材料层彼此平行或连续地由接触结构和至少一个上金属层。附加接触结构可以将电路连接到一个或多个上金属层。可以使用常规的处理步骤与3D存储器阵列同时地制造无源器件。

6. 发明授权

US08406063B2 Programming non-volatile storage with synchonized coupling 有权
标题翻译：用同步耦合编程非易失性存储器
公开(公告)号：US08406063B2
公开(公告)日：2013-03-26
申请号：US13590155
申请日：2012-08-20
申请人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
发明人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括为连接一组连接的非易失性存储元件的一组字线提升电压。所述字线组包括所选择的字线，与所选字线和其它未选字线相邻的未选字线。在提高该组字线的电压之后，该处理包括将所选择的字线升高到编程电压，并将与所选择的字线相邻的未选字线与提升所选择的字线同时提升到一个或多个电压电平到程序电压。程序电压使至少一个非易失性存储元件经历编程。

7. 发明申请

US20130070530A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20130070530A1
公开(公告)日：2013-03-21
申请号：US13622045
申请日：2012-09-18
申请人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

8. 发明申请

US20120314502A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING 有权
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：US20120314502A1
公开(公告)日：2012-12-13
申请号：US13590155
申请日：2012-08-20
申请人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
发明人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括为连接一组连接的非易失性存储元件的一组字线提升电压。所述字线组包括所选择的字线，与所选字线和其它未选字线相邻的未选字线。在提高该组字线的电压之后，该处理包括将所选择的字线升高到编程电压，并将与所选择的字线相邻的未选字线与提升所选择的字线同时提高到一个或多个电压电平到程序电压。程序电压使至少一个非易失性存储元件经历编程。

9. 发明授权

US08325529B2 Bit-line connections for non-volatile storage 有权
标题翻译：用于非易失性存储的位线连接
公开(公告)号：US08325529B2
公开(公告)日：2012-12-04
申请号：US12813437
申请日：2010-06-10
申请人： Chen-Che Huang , Chun-Ming Wang , Masaaki Higashitani
发明人： Chen-Che Huang , Chun-Ming Wang , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： H01L27/11551 , G11C16/0483 , H01L23/485 , H01L27/11519 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要： Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad.
摘要翻译：公开了用于非易失性存储装置的位线连接及其制造方法。可以在存储器单元和位线之间使用至少两种不同类型的位线连接。不同类型的位线连接可以在结构上彼此不同，如下所述。一种类型的位线连接可以包括在上通孔和下通孔之间的金属垫。另一种类型的位线连接可以包括上通孔和下通孔，但不包括金属垫。可以使用三排位线连接来放松间距。例如，外部的两行位线连接可以具有金属焊盘，而中间行中的位线连接不具有金属焊盘。

10. 发明授权

US08194470B2 Methods of forming flash device with shared word lines 有权
标题翻译：用共享字线形成闪存设备的方法
公开(公告)号：US08194470B2
公开(公告)日：2012-06-05
申请号：US12641113
申请日：2009-12-17
申请人： Masaaki Higashitani
发明人： Masaaki Higashitani
IPC分类号： G11C7/02 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11543
摘要： Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.
摘要翻译： NAND闪速存储器阵列的字线由同心的矩形形状的闭环形成，其具有大约是所使用的图案化工艺的最小特征尺寸的一半的宽度。所得到的电路具有连接在一起的字线，使得外围电路被共享。单独的擦除块由屏蔽板建立。

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