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1. 发明授权

US07420199B2 Resistivity changing memory cell having nanowire electrode 失效
标题翻译：具有纳米线电极的电阻率变化记忆单元
公开(公告)号：US07420199B2
公开(公告)日：2008-09-02
申请号：US11182022
申请日：2005-07-14
申请人： Martin Ulrich Gutsche , Harald Seidl , Franz Kreupl
发明人： Martin Ulrich Gutsche , Harald Seidl , Franz Kreupl
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , G11C13/0004 , G11C13/025 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.
摘要翻译：存储单元包括在第一电极和第二电极之间包括纳米线，第二电极和相变材料的第一电极。

2. 发明授权

US09177995B2 Vertical interconnect structure, memory device and associated production method 有权
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US09177995B2
公开(公告)日：2015-11-03
申请号：US13591247
申请日：2012-08-22
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L27/10 , H01L27/24 , H01L21/285 , H01L27/108 , B82Y10/00 , H01L21/768 , H01L27/22
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

3. 发明申请

US20070105333A1 Vertical interconnect structure, memory device and associated production method 有权
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US20070105333A1
公开(公告)日：2007-05-10
申请号：US11588769
申请日：2006-10-27
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

4. 发明授权

US08298932B2 Vertical interconnect structure, memory device and associated production method 有权
公开(公告)号：US08298932B2
公开(公告)日：2012-10-30
申请号：US13167744
申请日：2011-06-24
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L21/4763
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

5. 发明申请

US20110248234A1 VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD 有权
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US20110248234A1
公开(公告)日：2011-10-13
申请号：US13167744
申请日：2011-06-24
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L29/02 , H01L21/336 , H01L29/772
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储器件及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

6. 发明授权

US07998858B2 Vertical interconnect structure, memory device and associated production method 有权
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US07998858B2
公开(公告)日：2011-08-16
申请号：US11588769
申请日：2006-10-27
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L21/4763
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

7. 发明授权

US08420526B2 Vertical interconnect structure, memory device and associated production method 有权
公开(公告)号：US08420526B2
公开(公告)日：2013-04-16
申请号：US13167744
申请日：2011-06-24
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L21/4763
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

8. 发明申请

US20120305873A1 VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD 审中-公开
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US20120305873A1
公开(公告)日：2012-12-06
申请号：US13591247
申请日：2012-08-22
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L45/00
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

9. 发明申请

US20070012956A1 Phase change memory cell having nanowire electrode 失效
标题翻译：具有纳米线电极的相变存储单元
公开(公告)号：US20070012956A1
公开(公告)日：2007-01-18
申请号：US11182022
申请日：2005-07-14
申请人： Martin Gutsche , Harald Seidl , Franz Kreupl
发明人： Martin Gutsche , Harald Seidl , Franz Kreupl
IPC分类号： H01L29/768
CPC分类号： B82Y10/00 , G11C13/0004 , G11C13/025 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.
摘要翻译：存储单元包括在第一电极和第二电极之间包括纳米线，第二电极和相变材料的第一电极。

10. 发明申请

US20100006983A1 PROCESS FOR PRODUCING SUBLITHOGRAPHIC STRUCTURES 有权
标题翻译：生产分层结构的方法
公开(公告)号：US20100006983A1
公开(公告)日：2010-01-14
申请号：US12548723
申请日：2009-08-27
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L29/00
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/30604
摘要： A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures
摘要翻译：提供了用于提供亚光刻结构的层结构和工艺。在载体层的表面上形成第一辅助层。在第一辅助层的表面上形成光刻图案化的第二辅助层结构。使用图案化的第二辅助层结构作为掩模对第一辅助层进行各向异性蚀刻，以形成各向异性图案化的第一辅助层结构。各向异性图案化的第一辅助层结构使用图案化的第二辅助层结构进行各向同性地回蚀，以除去第二辅助层结构之下的部分并形成各向同性图案化的第一辅助层结构。掩模层形成在载体层上，包括第二辅助层结构下面的子部分，并且各向异性地向下蚀刻到载体层以形成亚光刻结构。去除第一和第二辅助层结构以露出亚光刻结构

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