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1. 发明授权

US06989311B2 Method for fabricating a trench contact to a deep trench capacitor having a polysilicon filling 失效
公开(公告)号：US06989311B2
公开(公告)日：2006-01-24
申请号：US10147544
申请日：2002-05-16
申请人： Martin Schrems , Dietmar Temmler , Andreas Wich-Glasen
发明人： Martin Schrems , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L21/76897
摘要： The instant invention is a method for fabricating a trench contact to a deep trench capacitor with a polysilicon filling in a trench hole formed in a silicon substrate. An epitaxy process is performed to selectively grow silicon above the polysilicon filling in the trench hole. An opening leading to the polysilicon filling is anisotropically etched into the epitaxially grown silicon. The opening has lateral dimensions that are smaller than those of the polysilicon filling, and the opening is filled with polysilicon.

2. 发明申请

US20060231918A1 Field effect transistor and method for the production thereof 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20060231918A1
公开(公告)日：2006-10-19
申请号：US10482328
申请日：2002-06-19
申请人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
发明人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L29/00
CPC分类号： H01L29/7851 , H01L21/76229 , H01L21/823481 , H01L29/0653 , H01L29/66651
摘要： A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.
摘要翻译：提供了一种晶体管，其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。在这种情况下，可以以自对准的方式扩大通道宽度，而不会出现短路的风险。根据本发明的场效应晶体管的优点在于，与先前使用的传统晶体管结构相比，可以确保正向电流ION的有效沟道宽度的显着增加，而不必接受集成密度的降低可以实现。因此，作为示例，正向电流I ON ON可以增加高达50％，而不必改变有源区域或沟槽隔离的布置。

3. 发明授权

US07294902B2 Trench isolation having a self-adjusting surface seal and method for producing one such trench isolation 有权
标题翻译：具有自调节表面密封的沟槽隔离和用于产生一个这种沟槽隔离的方法
公开(公告)号：US07294902B2
公开(公告)日：2007-11-13
申请号：US10485984
申请日：2002-07-24
申请人： Dietmar Temmler , Andreas Wich-Glasen
发明人： Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L29/00
CPC分类号： H01L21/76229
摘要： The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.
摘要翻译：本发明涉及具有自对准表面密封的沟槽隔离和用于所述表面密封的制造方法。在这种情况下，表面密封可以具有衬底表面的重叠区域或者形成在衬底表面上的导电层延伸的后退区域。

4. 发明申请

US20060231874A1 Field effect transistor and method for fabricating it 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20060231874A1
公开(公告)日：2006-10-19
申请号：US11294380
申请日：2005-12-06
申请人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
发明人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L29/76 , H01L29/94 , H01L21/8234 , H01L21/336 , H01L31/00
CPC分类号： H01L29/7851 , H01L21/76229 , H01L21/823481 , H01L29/0653 , H01L29/66651
摘要： A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.
摘要翻译：提供了一种晶体管，其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。在这种情况下，可以以自对准的方式扩大通道宽度，而不会出现短路的风险。根据本发明的场效应晶体管的优点在于，与先前使用的常规晶体管结构相比，可以确保正向电流I ON ON的有效沟道宽度的显着增加，而没有以接受可以实现的积分密度的降低。因此，作为示例，正向电流I ON ON可以增加高达50％，而不必改变有源区域或沟槽隔离的布置。

5. 发明授权

US07223651B2 Dram memory cell with a trench capacitor and method for production thereof 失效
标题翻译：具有沟槽电容器的大容量存储单元及其制造方法
公开(公告)号：US07223651B2
公开(公告)日：2007-05-29
申请号：US10479522
申请日：2002-06-05
申请人： Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
发明人： Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L21/8234
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/10873
摘要： A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor and a drain region connected to a bit line. The junction depth of the source region is chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.
摘要翻译：存储单元包括选择晶体管和沟槽电容器。沟槽电容器填充有绝缘覆盖层布置在其上的导电沟槽填充物。绝缘覆盖层横向长满，从具有选择性生长的外延层的衬底开始。选择晶体管形成在选择性生长的外延层中，包括连接到沟槽电容器的源极区域和连接到位线的漏极区域。选择源极区域的结深度，使得源极区域达到绝缘覆盖层的深度。任选地，可以通过氧化和随后的蚀刻将外延层的厚度减小到厚度。之后，接触沟槽通过源极区域被蚀刻到导电沟槽填充物，该沟槽填充有导电接触并将导电沟槽填充物电连接到源极区域。

6. 发明授权

US07119384B2 Field effect transistor and method for fabricating it 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07119384B2
公开(公告)日：2006-10-10
申请号：US10482331
申请日：2002-06-25
申请人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
发明人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7854 , H01L29/66484 , H01L29/66795 , H01L29/7831 , H01L29/7851
摘要： The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.
摘要翻译：本发明涉及一种场效应晶体管，其中，通过在该高度的侧面上的另外的垂直沟道区，在该高度的上表面上的平面通道区域的宽度被延伸。所述另外的垂直通道区域直接连接到平面通道区域（垂直扩展通道区域）。所述场效应晶体管的优点在于，相对于直到现在使用的常规晶体管结构，可以保证电流I ON的有效沟道宽度的显着增加，而不必接受可实现的集成密度。所述场效应晶体管还具有低反向电流I OFF。实现上述优点，而不必使栅极绝缘体的厚度直到电荷转移隧道的区域必须减小或稳定性降低。

7. 发明申请

US20050040134A1 Trench isolation having a self-adjusting surface seal and method for producing one such trench isolation 有权
标题翻译：具有自调节表面密封的沟槽隔离和用于产生一个这种沟槽隔离的方法
公开(公告)号：US20050040134A1
公开(公告)日：2005-02-24
申请号：US10485984
申请日：2002-07-24
申请人： Dietmar Temmler , Andreas Wich-Glasen
发明人： Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L21/762 , H01B13/00
CPC分类号： H01L21/76229
摘要： The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.
摘要翻译：本发明涉及具有自对准表面密封的沟槽隔离和用于所述表面密封的制造方法。在这种情况下，表面密封可以具有衬底表面的重叠区域或者形成在衬底表面上的导电层延伸的后退区域。

8. 发明申请

US20050029583A1 Field effect transistor and method for production thereof 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050029583A1
公开(公告)日：2005-02-10
申请号：US10482331
申请日：2002-06-25
申请人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
发明人： Martin Popp , Frank Richter , Dietmar Temmler , Andreas Wich-Glasen
IPC分类号： H01L29/423 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7854 , H01L29/66484 , H01L29/66795 , H01L29/7831 , H01L29/7851
摘要： The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.
摘要翻译：本发明涉及一种场效应晶体管，其中，通过在该高度的侧面上的另外的垂直沟道区，在该高度的上表面上的平面通道区域的宽度被延伸。所述另外的垂直通道区域直接连接到平面通道区域（垂直扩展通道区域）。所述场效应晶体管的优点在于，相对于直到现在使用的常规晶体管结构，可以保证电流ION的有效沟道宽度的显着增加，而不必接受可实现的积分密度的降低。所述场效应晶体管还具有低反向电流IOFF。实现上述优点，而不必使栅极绝缘体的厚度直到电荷转移隧道的区域必须减小或稳定性降低。

9. 发明授权

US07049647B2 Semiconductor memory cell with trench capacitor and selection transistor and method for fabricating it 失效
公开(公告)号：US07049647B2
公开(公告)日：2006-05-23
申请号：US10390871
申请日：2003-03-17
申请人： Wolfram Karcher , Dietmar Temmler , Martin Schrems
发明人： Wolfram Karcher , Dietmar Temmler , Martin Schrems
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor dielectric and a conductive trench filling. Disposed on the conductive trench filling is a diffusion barrier on which an epitaxial layer is formed. The selection transistor is disposed as a planar transistor above the trench capacitor. A drain doping region of the selection transistor is disposed in the epitaxial layer.

10. 发明授权

US06828192B2 Semiconductor memory cell and method for fabricating the memory cell 失效
标题翻译：半导体存储单元及其制造方法
公开(公告)号：US06828192B2
公开(公告)日：2004-12-07
申请号：US10657928
申请日：2003-09-10
申请人： Wolfgang Gustin , Ulrike Grüning-Von Schwerin , Dietmar Temmler , Martin Schrems , Stefan Rongen , Rudolf Strasser
发明人： Wolfgang Gustin , Ulrike Grüning-Von Schwerin , Dietmar Temmler , Martin Schrems , Stefan Rongen , Rudolf Strasser
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10873
摘要： A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.
摘要翻译：在沟槽中形成沟槽电容器，其设置在基板中。沟槽填充有用作内部电容器电极的导电沟槽填充物。在衬底上的沟槽的侧壁上生长外延层。掩埋带设置在填充有第二中间层的导电沟槽和外延生长层之间。在外延生长层中设置从掩埋带形成的掺杂剂外扩散。通过外延生长层，从布置在沟槽旁边的选择晶体管进一步去除掺杂剂扩散，结果可以避免选择晶体管中的短沟道效应。

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