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1. 发明授权

US07385536B2 Methods and circuits for output of sample-and-hold in pipelined ADC 有权
标题翻译：流水线ADC中采样和保持输出的方法和电路
公开(公告)号：US07385536B2
公开(公告)日：2008-06-10
申请号：US11012015
申请日：2004-12-14
申请人： Martin Kithinji Kinyua , Franco Maloberti
发明人： Martin Kithinji Kinyua , Franco Maloberti
IPC分类号： H03M1/00
CPC分类号： G11C27/026 , H03M1/1245 , H03M1/164 , H03M1/442
摘要： Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold signal path for use in a pipelined ADC includes a sample-and-hold circuit configured to operate in two distinct phases. The sample-and-hold circuit includes an input node, an output node, and a power supply node. The power supply node is configured to power down the op amp during one phase and power up the op amp during the other phase. The sample-and-hold stage is configured to provide output during one phase only. Other aspects of the invention include embodiments in which a sample-and-hold stage signal path in a pipelined analog-to-digital converter is configured to accommodate a plurality of parallel outputs.
摘要翻译：公开了实现用于采样和保持输出的改进的信号路径的方法和电路实施例。在示例性实施例中，用于流水线式ADC的采样和保持信号路径包括被配置为在两个不同阶段中操作的采样和保持电路。采样和保持电路包括输入节点，输出节点和电源节点。电源节点配置为在一个阶段关闭运算放大器，并在另一阶段加电运算放大器。采样和保持级配置为仅在一个阶段提供输出。本发明的其它方面包括其中流水线模数转换器中的采样保持级信号路径被配置为容纳多个并行输出的实施例。

2. 发明授权

US07107175B2 Continuous digital background calibration in pipelined ADC architecture 有权
公开(公告)号：US07107175B2
公开(公告)日：2006-09-12
申请号：US11251668
申请日：2005-10-17
申请人： Franco Maloberti , Martin Kithinji Kinyua
发明人： Franco Maloberti , Martin Kithinji Kinyua
IPC分类号： G06F19/00 , H03M1/10
CPC分类号： H03M1/1004 , H03M1/145
摘要： Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

3. 发明授权

US07035756B2 Continuous digital background calibration in pipelined ADC architecture 有权
标题翻译：流水线ADC结构中的连续数字背景校准
公开(公告)号：US07035756B2
公开(公告)日：2006-04-25
申请号：US10738751
申请日：2003-12-17
申请人： Franco Maloberti , Martin Kithinji Kinyua
发明人： Franco Maloberti , Martin Kithinji Kinyua
IPC分类号： G06F19/00 , H03M1/10
CPC分类号： H03M1/1004 , H03M1/145
摘要： Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.
摘要翻译：公开了用于在流水线ADC系统中实现校准的新方法和系统。方法和系统可用于在流水线ADC中提供连续数字背景校准。流水线中每个DAC的组件不匹配错误列表，以提供从ADC传输特性中减去的积分非线性配置文件。

4. 发明授权

US06958723B1 Method and apparatus for reducing noise in analog-to-digital converter devices 有权
标题翻译：降低模数转换器装置噪声的方法和装置
公开(公告)号：US06958723B1
公开(公告)日：2005-10-25
申请号：US10803128
申请日：2004-03-17
申请人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
发明人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
IPC分类号： H03M1/08 , H03M1/38 , H03M1/44
CPC分类号： H03M1/08 , H03M1/447
摘要： An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.
摘要翻译：模数转换器装置具有多个级。每个级包括具有第一和第二放大器单元的残余放大器。每个放大器单元具有第一输入轨迹，第二输入轨迹和输出轨迹。放大器单元合作在第一输入轨迹处接收差分输入数据信号。 DC电平设定信号单元与第二输入轨迹耦合，并且在第一电流方向上提供直流电平设定电流。逆流信号产生单元经由与第二输入轨迹共同的单个耦合轨迹与第二输入轨迹耦合，并且在与第一电流方向相反的第二电流方向上向第二输入轨迹提供控制电流信号。控制电流信号为每个放大器单元提供直流电平控制。

5. 发明授权

US07432841B1 Delta-sigma analog-to-digital converter with pipelined multi-bit quantization 有权
标题翻译：具有流水线多位量化的Delta-sigma模数转换器
公开(公告)号：US07432841B1
公开(公告)日：2008-10-07
申请号：US11807504
申请日：2007-05-29
申请人： Martin Kithinji Kinyua
发明人： Martin Kithinji Kinyua
IPC分类号： H03M3/00
CPC分类号： H03M3/414
摘要： A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A second, coupled multi-stage delta-sigma modulator quantizes less significant bits of the input signal, wherein a first quantization stage is coupled to the first quantization error signal to quantize the next most significant bits of the input signal and produce a second quantization error signal. A second quantization stage is coupled to the second quantization error signal to quantize the least significant bits of the input signal and produce a third quantization error signal. A noise-shaping filter is coupled to the third quantization error signal, the output of which is subtracted from the first quantization error signal to produce said input of the first quantization stage.
摘要翻译：级联的模数转换器包括用于量化输入信号并产生第一量化误差信号的第一级Δ-Σ调制器。第二耦合多级Δ-Σ调制器量化输入信号的较低有效位，其中第一量化级耦合到第一量化误差信号以量化输入信号的下一个最高有效位并产生第二量化误差信号。第二量化级耦合到第二量化误差信号以量化输入信号的最低有效位并产生第三量化误差信号。噪声整形滤波器耦合到第三量化误差信号，其输出从第一量化误差信号中减去以产生第一量化级的所述输入。

6. 发明授权

US07292170B2 System and method for improved time-interleaved analog-to-digital converter arrays 有权
标题翻译：用于改进时间交织的模数转换器阵列的系统和方法
公开(公告)号：US07292170B2
公开(公告)日：2007-11-06
申请号：US11151133
申请日：2005-06-13
申请人： Martin Kithinji Kinyua , William J. Bright
发明人： Martin Kithinji Kinyua , William J. Bright
IPC分类号： H03M3/00
CPC分类号： H03M1/0624 , H03M1/1215
摘要： System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.
摘要翻译：用于改进时间交织的模数转换器阵列的系统和方法，其减少了现有技术阵列中发现的采样失配失真。在TI-ADC阵列中可能存在两个非均匀采样不匹配的原因：由于偏移引起的失配和由于时钟抖动导致的失配。为了最小化非均匀采样不匹配，可以解决由于偏斜引起的失配。优选实施例包括在TI-ADC阵列中的多个通道的每个通道中调整在采样时钟上施加的延迟一个可调节的延迟，以最小化偏差并在跨越零偏移延迟的两个延迟之间随机切换以减少残余偏斜从而消除（或减少）由不均匀采样失配引起的频域色调。

7. 发明授权

US06856188B2 Current source/sink with high output impedance using bipolar transistors 有权
标题翻译：使用双极晶体管的具有高输出阻抗的电流源/宿
公开(公告)号：US06856188B2
公开(公告)日：2005-02-15
申请号：US10447176
申请日：2003-05-28
申请人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua
发明人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua
IPC分类号： H03F1/22 , G05F3/26 , G05F1/10
CPC分类号： G05F3/265
摘要： A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by directing a compensation current corresponding to change in base current in the cascode (Q1) in an approach such that the compensation current cancels out the error of the cascode (Q1). In a further example, biasing circuitry (200) is included and arranged such that change in base current of the cascode (Q1) is detected and a corresponding current is summed at the emitter of the cascode (Q1) such that the collector current of the cascode (Q1) remains unchanged.
摘要翻译：提供具有高输出阻抗的共源共栅电流源/宿的电路和方法。在一个示例中，通过在使得补偿电流消除共源共栅（Q1）的误差的方法中引导与共源共栅（Q1）中的基极电流的变化相对应的补偿电流来减小对外部负载的依赖性。在另一示例中，偏置电路（200）被包括并布置成使得检测到共源共栅（Q1）的基极电流的变化，并且在共源共栅（Q1）的发射极处对应的电流相加，使得共源共栅（Q1）保持不变。

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