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1. 发明申请

US20100283107A1 MOS Transistor With Better Short Channel Effect Control and Corresponding Manufacturing Method 审中-公开
标题翻译：具有更好的短沟道效应控制的MOS晶体管和相应的制造方法
公开(公告)号：US20100283107A1
公开(公告)日：2010-11-11
申请号：US12086561
申请日：2006-12-07
申请人： Markus Muller , Alexandre Mondot , Arnaud Pouydebasque
发明人： Markus Muller , Alexandre Mondot , Arnaud Pouydebasque
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/823835 , H01L21/823842
摘要： The integrated circuit comprises at least one MOS transistor (T) including a gate (GR) having a bottom part in contact with the gate oxide. Said bottom part has an inhomogeneous work function (WFB, WFA) along the length of the gate between the source and drain regions, the value of the work function being greater at the extremities of the gate than in the centre of the gate. The gate comprises a first material (A) in the centre and a second material (B) in the remaining part. Such configuration is obtained for example by silicidation.
摘要翻译：集成电路包括至少一个MOS晶体管（T），其包括具有与栅极氧化物接触的底部的栅极（GR）。所述底部部分沿源极和漏极区域之间的栅极长度具有不均匀的功函数（WFB，WFA），在栅极的末端，功函数值大于栅极中心的值。该门包括中心的第一材料（A）和剩余部分中的第二材料（B）。这种配置例如通过硅化获得。

2. 发明授权

US08551352B2 Method for producing a device with a fluid-encapsulating membrane 有权
标题翻译：用流体封装膜制造器件的方法
公开(公告)号：US08551352B2
公开(公告)日：2013-10-08
申请号：US13177840
申请日：2011-07-07
申请人： Arnaud Pouydebasque , Sébastien Bolis , Fabrice Jacquet
发明人： Arnaud Pouydebasque , Sébastien Bolis , Fabrice Jacquet
IPC分类号： C03C15/00
CPC分类号： G02B3/14 , F04B43/043 , G02B26/004
摘要： The invention relates to a method for producing a device with a membrane used to encapsulate a fluid contained in a cavity, in which: two substrates (110, 120) are provided; a membrane (111) is placed on one and/or on the other of the substrates; one or more walls (113) are formed, helping to laterally define the cavity (114), in which said walls are located on or in one of the substrates and/or on or in the other of the substrates, and said cavity is intended to contain the fluid, the two substrates (110, 120) are assembled together by superimposing one on the other so as to complete the cavity, in which the or each membrane (111) also helps to define the cavity, the fluid (117) is encapsulated in the cavity between the substrates, and the or each membrane is soaked by the fluid, at least a portion of one of the substrates and/or the other of the substrates is removed insofar as one and/or the other of the substrates are equipped with a membrane, in order to release the membrane at least in the central portion thereof.
摘要翻译：本发明涉及一种用于制造具有用于封装包含在空腔中的流体的膜的装置的方法，其中：设置两个基板（110,120）; 膜（111）被放置在基板的一个和/或另一个上; 形成一个或多个壁（113），有助于横向限定空腔（114），其中所述壁位于其中一个基板上和/或其中一个基板上和/或其中一个基板上，并且所述空腔旨在为了容纳流体，通过将两个基板（110,120）叠置在另一个上以便完成空腔（其中所述隔膜（111）也有助于限定空腔），所述流体（117）被封装在基板之间的空腔中，并且每个膜被流体浸泡，至少一部分基板和/或另一个基板被去除，只要一个和/或另一个基板配备有膜，以便至少在其中心部分释放膜。

3. 发明授权

US07687356B2 Formation of shallow siGe conduction channel 有权
标题翻译：浅层导电通道的形成
公开(公告)号：US07687356B2
公开(公告)日：2010-03-30
申请号：US11714063
申请日：2007-03-05
申请人： Philippe Coronel , Arnaud Pouydebasque
发明人： Philippe Coronel , Arnaud Pouydebasque
IPC分类号： H01L21/336
CPC分类号： H01L29/78684 , H01L21/385
摘要： A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.
摘要翻译：一种在半导体器件的栅堆叠下形成硅锗导电沟道的方法，所述栅叠层形成在绝缘层上的硅层上，所述方法包括在所述硅层上生长硅锗层并加热所述器件，使得锗在硅层中冷凝，使得在栅极堆叠和绝缘层之间形成硅锗沟道。

4. 发明授权

US08013399B2 SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable 有权
标题翻译： SRAM存储单元具有以多个级别集成的晶体管，其阈值电压VT可动态调整
公开(公告)号：US08013399B2
公开(公告)日：2011-09-06
申请号：US12466733
申请日：2009-05-15
申请人： Olivier Thomas , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
发明人： Olivier Thomas , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.
摘要翻译：一种静态随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平，其中至少一个第一存取晶体管和至少一个第二存取晶体管连接分别布置在第一位线和第一存储节点以及第二位线和第二存储节点之间; 以及第二多个晶体管，其形成触发器并且位于所述给定电平以下的所述堆叠的至少另一个电平，其中所述第二多个晶体管的晶体管每个包括位于与所述晶体管的晶体管的沟道区相对的栅电极所述第一多个晶体管并且由所述沟道区域与被设置成能够耦合所述栅极电极和所述沟道区域的绝缘区域分离。

5. 发明授权

US07960255B2 Process for forming a wire portion in an integrated electronic circuit 有权
标题翻译：在集成电子电路中形成导线部分的工艺
公开(公告)号：US07960255B2
公开(公告)日：2011-06-14
申请号：US12679882
申请日：2008-09-22
申请人： Philippe Coronel , Benjamin Dumont , Arnaud Pouydebasque , Markus Müller
发明人： Philippe Coronel , Benjamin Dumont , Arnaud Pouydebasque , Markus Müller
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/762
摘要： A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.
摘要翻译：在集成电子电路中形成导线部分的工艺包括在晶种层部分（11,12）的侧表面上外延生长导线部分。线部分的横截面尺寸对应于种子层部分的厚度和生长步骤的持续时间。然后选择性地去除晶种层部分，同时线部分固定地保持在电路上。之后，电路的加热会导致导线部分的横截面变圆。获得的导线部分的直径可以为约10纳米。它可以用于形成没有短沟道效应的MOS晶体管的沟道。

6. 发明申请

US20120006783A1 METHOD FOR PRODUCING A DEVICE WITH A FLUID-ENCAPSULATING MEMBRANE 有权
标题翻译：用流体包封膜生产装置的方法
公开(公告)号：US20120006783A1
公开(公告)日：2012-01-12
申请号：US13177840
申请日：2011-07-07
申请人： Arnaud Pouydebasque , Sébastien Bolis , Fabrice Jacquet
发明人： Arnaud Pouydebasque , Sébastien Bolis , Fabrice Jacquet
IPC分类号： C03C25/68 , B29C65/00
CPC分类号： G02B3/14 , F04B43/043 , G02B26/004
摘要： The invention relates to a method for producing a device with a membrane used to encapsulate a fluid contained in a cavity, in which: two substrates (110, 120) are provided; a membrane (111) is placed on one and/or on the other of the substrates; one or more walls (113) are formed, helping to laterally define the cavity (114), in which said walls are located on or in one of the substrates and/or on or in the other of the substrates, and said cavity is intended to contain the fluid, the two substrates (110, 120) are assembled together by superimposing one on the other so as to complete the cavity, in which the or each membrane (111) also helps to define the cavity, the fluid (117) is encapsulated in the cavity between the substrates, and the or each membrane is soaked by the fluid, at least a portion of one of the substrates and/or the other of the substrates is removed insofar as one and/or the other of the substrates are equipped with a membrane, in order to release the membrane at least in the central portion thereof.
摘要翻译：本发明涉及一种用于制造具有用于封装包含在空腔中的流体的膜的装置的方法，其中：设置两个基板（110,120）; 膜（111）被放置在基板的一个和/或另一个上; 形成一个或多个壁（113），有助于横向限定空腔（114），其中所述壁位于其中一个基板上和/或其中一个基板上和/或其中一个基板上，并且所述空腔旨在为了容纳流体，通过将两个基板（110,120）叠置在另一个上以便完成空腔（其中所述隔膜（111）也有助于限定空腔），所述流体（117）被封装在基板之间的空腔中，并且每个膜被流体浸泡，至少一部分基板和/或另一个基板被去除，只要一个和/或另一个基板配备有膜，以便至少在其中心部分释放膜。

7. 发明申请

US20100203712A1 PROCESS FOR FORMING A WIRE PORTION IN AN INTEGRATED ELECTRONIC CIRCUIT 有权
标题翻译：在一体化电子电路中形成电线部分的方法
公开(公告)号：US20100203712A1
公开(公告)日：2010-08-12
申请号：US12679882
申请日：2008-09-22
申请人： Philippe Coronel , Benjamin Dumont , Arnaud Pouydebasque , Markus Müller
发明人： Philippe Coronel , Benjamin Dumont , Arnaud Pouydebasque , Markus Müller
IPC分类号： H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/762
摘要： A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.
摘要翻译：在集成电子电路中形成导线部分的工艺包括在晶种层部分（11,12）的侧表面上外延生长导线部分。线部分的横截面尺寸对应于种子层部分的厚度和生长步骤的持续时间。然后选择性地去除晶种层部分，同时线部分固定地保持在电路上。之后，电路的加热会导致导线部分的横截面变圆。获得的导线部分的直径可以为约10纳米。它可以用于形成没有短沟道效应的MOS晶体管的沟道。

8. 发明申请

US20070275513A1 Formation of shallow siGe conduction channel 有权
标题翻译：浅层导电通道的形成
公开(公告)号：US20070275513A1
公开(公告)日：2007-11-29
申请号：US11714063
申请日：2007-03-05
申请人： Philippe Coronel , Arnaud Pouydebasque
发明人： Philippe Coronel , Arnaud Pouydebasque
IPC分类号： H01L21/336
CPC分类号： H01L29/78684 , H01L21/385
摘要： The invention concerns a method of forming a silicon germanium conduction channel under a gate stack (6) of a semiconductor device, the gate stack being formed on a silicon layer (4) on an insulating layer (2), the method comprising: growing a silicon germanium layer (14) over said silicon layer; and heating the device such that germanium condenses in said silicon layer (4) such that a silicon germanium channel (18) is formed between said gate stack and said insulating layer.
摘要翻译：本发明涉及一种在半导体器件的栅叠层（6）下方形成硅锗导电沟道的方法，该栅叠层形成在绝缘层（2）上的硅层（4）上，该方法包括：所述硅层上的硅锗层（14）; 以及加热所述器件，使得锗在所述硅层（4）中冷凝，使得在所述栅叠层和所述绝缘层之间形成硅锗沟道（18）。

9. 发明授权

US07923315B2 Manufacturing method for planar independent-gate or gate-all-around transistors 有权
标题翻译：平面独立栅极或栅极全环晶体管的制造方法
公开(公告)号：US07923315B2
公开(公告)日：2011-04-12
申请号：US12809876
申请日：2008-12-18
申请人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
发明人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/66484 , H01L29/66636 , H01L29/7831 , H01L29/78654
摘要： The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.
摘要翻译：本发明涉及一种在体半导体衬底上制造平面独立双栅极FET或平面栅极全周围FET的方法。该方法包括在有源半导体区域中用掩埋牺牲层重新填充表面凹槽，并且在通过相应的沉积和图案化准备预处理栅极堆叠之后，在隔离区域中形成凹槽，以便使凹部在指向内衬底的深度方向上延伸到允许去除掩埋牺牲层的深度水平，并且使得凹槽在通道方向上削弱栅极堆叠的部分。

10. 发明申请

US20110014769A1 MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS 有权
标题翻译：平面独立门或门极绕线晶体管的制造方法
公开(公告)号：US20110014769A1
公开(公告)日：2011-01-20
申请号：US12809876
申请日：2008-12-18
申请人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
发明人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/66484 , H01L29/66636 , H01L29/7831 , H01L29/78654
摘要： The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.
摘要翻译：本发明涉及一种在体半导体衬底上制造平面独立双栅极FET或平面栅极全周围FET的方法。该方法包括在有源半导体区域中用掩埋牺牲层重新填充表面凹槽，并且在通过相应的沉积和图案化准备预处理栅极堆叠之后，在隔离区域中形成凹槽，以便使凹部在指向内衬底的深度方向上延伸到允许去除掩埋牺牲层的深度水平，并且使得凹槽在通道方向上削弱栅极堆叠的部分。

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