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1. 发明授权

US08013399B2 SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable 有权
标题翻译： SRAM存储单元具有以多个级别集成的晶体管，其阈值电压VT可动态调整
公开(公告)号：US08013399B2
公开(公告)日：2011-09-06
申请号：US12466733
申请日：2009-05-15
申请人： Olivier Thomas , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
发明人： Olivier Thomas , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.
摘要翻译：一种静态随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平，其中至少一个第一存取晶体管和至少一个第二存取晶体管连接分别布置在第一位线和第一存储节点以及第二位线和第二存储节点之间; 以及第二多个晶体管，其形成触发器并且位于所述给定电平以下的所述堆叠的至少另一个电平，其中所述第二多个晶体管的晶体管每个包括位于与所述晶体管的晶体管的沟道区相对的栅电极所述第一多个晶体管并且由所述沟道区域与被设置成能够耦合所述栅极电极和所述沟道区域的绝缘区域分离。

2. 发明申请

US20090294861A1 SRAM MEMORY CELL HAVING TRANSISTORS INTEGRATED AT SEVERAL LEVELS AND THE THRESHOLD VOLTAGE VT OF WHICH IS DYNAMICALLY ADJUSTABLE 有权
标题翻译：具有集成在几个级别的晶体管的SRAM存储单元和动态调整的阈值电压VT
公开(公告)号：US20090294861A1
公开(公告)日：2009-12-03
申请号：US12466733
申请日：2009-05-15
申请人： Olivier THOMAS , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
发明人： Olivier THOMAS , Perrine Batude , Arnaud Pouydebasque , Maud Vinet
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises:a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line,a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level,the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.
摘要翻译：一种非易失性随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平处，其中至少一个第一存取晶体管和至少一个第二存取晶体管，其分别布置在第一位线和第一存储节点之间，以及第二位线和第二存储节点之间，第一存取晶体管和第二存取晶体管具有连接到字线的栅极，第二多个形成触发器并且位于所述堆叠的至少另一个层级下面的所述给定电平以下的所述第二多个晶体管的晶体管分别包括与所述第一多个晶体管的沟道区相对的栅电极的晶体管，并且通过提供用于使得所述栅极电极和所述沟道区域耦合的绝缘区域与该沟道区域分离。

3. 发明授权

US08183630B2 Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT 有权
标题翻译：具有集成在三维中并具有动态可调阈值电压VT的晶体管的电路
公开(公告)号：US08183630B2
公开(公告)日：2012-05-22
申请号：US12474851
申请日：2009-05-29
申请人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
发明人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
IPC分类号： H01L29/66 , H01L29/94
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
摘要翻译：一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平处的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管包括与第二晶体管的沟道区相对的栅电极，第一晶体管和第二晶体管被绝缘区隔开，所述绝缘区由几种不同的介电材料构成，包括第一电介质材料和第二电介质材料。

4. 发明申请

US20090294822A1 CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT 有权
标题翻译：具有集成在三维尺寸并具有动态可调节阈值电压VT的晶体管的电路
公开(公告)号：US20090294822A1
公开(公告)日：2009-12-03
申请号：US12474851
申请日：2009-05-29
申请人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
发明人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.
摘要翻译：一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管包括与所述第二晶体管的沟道区相对的栅电极，所述第一晶体管和所述第二晶体管通过绝缘区隔开，所述绝缘区在所述第一晶体管的所述栅极和所述第一晶体管的所述沟道之间的第一区域中所述第二晶体管的组成和厚度设置成使得能够在所述第一晶体管的栅电极和所述第二晶体管的沟道之间的耦合，所述绝缘区包括所述第一区周围的第二区，以及第二晶体管的厚度和组成不同于所述第一区域的晶体管。

5. 发明申请

US20110147849A1 INTEGRATED CIRCUIT WITH ELECTROSTATICALLY COUPLED MOS TRANSISTORS AND METHOD FOR PRODUCING SUCH AN INTEGRATED CIRCUIT 有权
标题翻译：具有静电耦合MOS晶体管的集成电路和用于生产这种集成电路的方法
公开(公告)号：US20110147849A1
公开(公告)日：2011-06-23
申请号：US12868488
申请日：2010-08-25
申请人： Emmanuel AUGENDRE , Maud Vinet , Laurent Clavelier , Perrine Batude
发明人： Emmanuel AUGENDRE , Maud Vinet , Laurent Clavelier , Perrine Batude
IPC分类号： H01L27/088 , H01L21/98
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.
摘要翻译：一种集成电路，包括：第一晶体管; 第二晶体管，布置在第一晶体管上，沟道区形成在包括两个近似平行的主面的半导体层中; 导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且其中第二晶体管的沟道区域的部分包括在导电材料部分的部分中，并且第二晶体管的沟道区域被布置在导电材料的部分和栅极之间第二晶体管。

6. 发明授权

US08853785B2 Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit 有权
标题翻译：具有静电耦合MOS晶体管的集成电路及其制造方法
公开(公告)号：US08853785B2
公开(公告)日：2014-10-07
申请号：US12868488
申请日：2010-08-25
申请人： Emmanuel Augendre , Maud Vinet , Laurent Clavelier , Perrine Batude
发明人： Emmanuel Augendre , Maud Vinet , Laurent Clavelier , Perrine Batude
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
摘要翻译：一种集成电路，至少包括：第一MOS晶体管; 配置在所述第一MOS晶体管上的第二MOS晶体管，所述第二MOS晶体管在至少一个包含两个近似平行的主面的半导体层中包括沟道区; 至少一个导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 至少布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且在与半导体层的两个主面平行的平面中的第二晶体管的沟道区域的一部分被包括在投影在所述平面中的导电材料部分的一部分中。

7. 发明申请

US20130203248A1 INTEGRATED CIRCUIT HAVING A JUNCTIONLESS DEPLETION-MODE FET DEVICE 审中-公开
标题翻译：具有无连续截止模式FET器件的集成电路
公开(公告)号：US20130203248A1
公开(公告)日：2013-08-08
申请号：US13702226
申请日：2011-06-06
申请人： Thomas Ernst , Marie-Anne Jaud , Perrine Batude
发明人： Thomas Ernst , Marie-Anne Jaud , Perrine Batude
IPC分类号： H01L21/74
CPC分类号： H01L21/743 , H01L21/8221 , H01L21/823807 , H01L27/0688 , H01L27/11578 , H01L29/785 , H01L29/78696
摘要： A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer.
摘要翻译：一种用于制造集成电路的方法，包括以下顺序：a）在衬底上产生至少一个MOS电子电路和/或至少一个电互连级别; b）在晶体半导体层的至少一部分中均匀地注入掺杂剂; c）热激活注入在晶体半导体层的部分中的掺杂剂; d）将晶体半导体层刚性地连接到衬底; 以及e）产生包括所述结晶半导体层的所述部分的一部分的至少一个无结晶耗尽型FET器件。

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