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1. 发明申请

US20070045664A1 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20070045664A1
公开(公告)日：2007-03-01
申请号：US11485287
申请日：2006-07-13
申请人： Markoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
发明人： Markoto Miura , Katsuyoshi Washio , Hiromi Shimamoto
IPC分类号： H01L31/00
CPC分类号： H01L29/7378 , Y10S438/936
摘要： A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier generated upon increase of the collector current and enabling satisfactory transistor operation at high current.
摘要翻译：一种半导体器件及其制造方法，其能够在保持高耐受电压的同时避免在导带中产生阻挡层并能够在高电流下进行高速晶体管的操作，以及其制造方法，其中，集电体由禁带宽度窄于半导体衬底的材料形成，禁带从发射极侧向集电极侧逐步且连续地增加的区域设置在基体的内部，禁带在基极集电体界面的宽度被设计为大于基极中的最小禁带宽度，由此集电极侧的基底边缘处的禁带宽度可以更接近半导体的禁带宽度衬底，同时充分保持发射极基极附近的杂质效应，从而能够降低高度在集电极电流增加时产生能量势垒，并且能够在高电流下令人满意的晶体管工作。

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