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1. 发明申请

US20080135894A1 Transistor with improved tip profile and method of manufacture thereof 有权
标题翻译：具有改进尖端轮廓的晶体管及其制造方法
公开(公告)号：US20080135894A1
公开(公告)日：2008-06-12
申请号：US12009122
申请日：2008-01-15
申请人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
发明人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
IPC分类号： H01L29/94
CPC分类号： H01L29/045 , H01L21/30608 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
摘要翻译：实施例是改进的晶体管结构和制造该结构的方法。特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能并且在源极和漏极与硅化物之间的界面处降低接触电阻。

2. 发明授权

US07494858B2 Transistor with improved tip profile and method of manufacture thereof 有权
标题翻译：具有改进尖端轮廓的晶体管及其制造方法
公开(公告)号：US07494858B2
公开(公告)日：2009-02-24
申请号：US11173660
申请日：2005-06-30
申请人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
发明人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
IPC分类号： H01L21/336
CPC分类号： H01L29/045 , H01L21/30608 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
摘要翻译：实施例是改进的晶体管结构和制造该结构的方法。特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能并且在源极和漏极与硅化物之间的界面处降低接触电阻。

3. 发明授权

US07821044B2 Transistor with improved tip profile and method of manufacture thereof 有权
标题翻译：具有改进尖端轮廓的晶体管及其制造方法
公开(公告)号：US07821044B2
公开(公告)日：2010-10-26
申请号：US12009122
申请日：2008-01-15
申请人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
发明人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
IPC分类号： H01L21/336 , H01L29/06
CPC分类号： H01L29/045 , H01L21/30608 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
摘要翻译：实施例是改进的晶体管结构和制造该结构的方法。特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能并且在源极和漏极与硅化物之间的界面处降低接触电阻。

4. 发明授权

US08441097B2 Methods to form memory devices having a capacitor with a recessed electrode 有权
标题翻译：形成具有带有凹陷电极的电容器的存储器件的方法
公开(公告)号：US08441097B2
公开(公告)日：2013-05-14
申请号：US12646957
申请日：2009-12-23
申请人： Joseph M. Steigerwald , Nick Lindert , Steven J. Keating , Christopher J. Jezewski , Timothy E. Glassman
发明人： Joseph M. Steigerwald , Nick Lindert , Steven J. Keating , Christopher J. Jezewski , Timothy E. Glassman
IPC分类号： H01L21/02
CPC分类号： H01L28/90 , H01L27/0733
摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.
摘要翻译：描述形成具有凹陷电极的MIM电容器的存储器件的方法。在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

5. 发明申请

US20110147888A1 METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE 有权
标题翻译：用于形成具有电容器的电容器的存储器件的方法
公开(公告)号：US20110147888A1
公开(公告)日：2011-06-23
申请号：US12646957
申请日：2009-12-23
申请人： Joseph M. Steigerwald , Nick Lindert , Steven J. Keating , Christopher J. Jezewski , Timothy E. Glassman
发明人： Joseph M. Steigerwald , Nick Lindert , Steven J. Keating , Christopher J. Jezewski , Timothy E. Glassman
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L27/0733
摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.
摘要翻译：描述形成具有凹陷电极的MIM电容器的存储器件的方法。在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

6. 发明授权

US07927959B2 Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权
标题翻译：在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件
公开(公告)号：US07927959B2
公开(公告)日：2011-04-19
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L21/467
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

7. 发明授权

US06667232B2 Thin dielectric layers and non-thermal formation thereof 失效
标题翻译：形成薄栅极电介质层的方法
公开(公告)号：US06667232B2
公开(公告)日：2003-12-23
申请号：US09208268
申请日：1998-12-08
申请人： Steven J. Keating , Robert S. Chau , Reza Arghavani , Jack T. Kavalieros , Douglas W. Barlage
发明人： Steven J. Keating , Robert S. Chau , Reza Arghavani , Jack T. Kavalieros , Douglas W. Barlage
IPC分类号： H01L214763
CPC分类号： H01L21/0214 , H01L21/02329 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3143 , H01L29/51 , H01L29/518 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.
摘要翻译：形成适合用作MOSFET中的栅介质层的电介质层的方法包括在低于大约80℃的温度下钝化半导体衬底的表面并使钝化层氮化。在特定实施例中，钝化硅晶片包括在约24℃下形成羟基硅酸盐层。在本发明的另一方面，集成电路包括多个绝缘栅场效应晶体管，其中多个晶体管具有氮化钝化层的栅介质层。

8. 发明授权

US06953719B2 Integrating n-type and p-type metal gate transistors 有权
公开(公告)号：US06953719B2
公开(公告)日：2005-10-11
申请号：US10851360
申请日：2004-05-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

9. 发明授权

US06271096B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06271096B1
公开(公告)日：2001-08-07
申请号：US09458537
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

10. 发明授权

US06972225B2 integrating n-type and P-type metal gate transistors 有权
标题翻译：集成n型和P型金属栅极晶体管
公开(公告)号：US06972225B2
公开(公告)日：2005-12-06
申请号：US10946502
申请日：2004-09-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

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