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1. 发明授权

US07927959B2 Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权
标题翻译：在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件
公开(公告)号：US07927959B2
公开(公告)日：2011-04-19
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L21/467
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

2. 发明授权

US08441057B2 Embedded memory device having MIM capacitor formed in excavated structure 有权
公开(公告)号：US08441057B2
公开(公告)日：2013-05-14
申请号：US13028400
申请日：2011-02-16
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

3. 发明申请

US20100079924A1 Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权
标题翻译：在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件
公开(公告)号：US20100079924A1
公开(公告)日：2010-04-01
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01G4/008 , H01L21/311 , H01L21/20
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

4. 发明申请

US20130234290A1 METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY 有权
标题翻译：在金属切割特征的垂直平面上绘制金属的方法，使用其形成嵌入式MIM电容器的方法以及生产的嵌入式存储器件
公开(公告)号：US20130234290A1
公开(公告)日：2013-09-12
申请号：US13868273
申请日：2013-04-23
申请人： Steven Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

5. 发明申请

US20110134583A1 METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY 有权
标题翻译：在金属切割特征的垂直平面上绘制金属的方法，使用其形成嵌入式MIM电容器的方法以及生产的嵌入式存储器件
公开(公告)号：US20110134583A1
公开(公告)日：2011-06-09
申请号：US13028400
申请日：2011-02-16
申请人： Steve J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steve J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01G4/00
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分（435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料湿蚀刻化学。所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

6. 发明授权

US07709866B2 Method for forming semiconductor contacts 失效
标题翻译：半导体触点形成方法
公开(公告)号：US07709866B2
公开(公告)日：2010-05-04
申请号：US11821971
申请日：2007-06-26
申请人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
发明人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
IPC分类号： H01L29/51 , H01L21/469
CPC分类号： H01L21/76804 , H01L21/76816 , H01L29/78
摘要： In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
摘要翻译：在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

7. 发明申请

US20090001431A1 Method for forming semiconductor contacts 失效
标题翻译：半导体触点形成方法
公开(公告)号：US20090001431A1
公开(公告)日：2009-01-01
申请号：US11821971
申请日：2007-06-26
申请人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
发明人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76816 , H01L29/78
摘要： In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
摘要翻译：在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

8. 发明申请

US20070218685A1 Method of forming trench contacts for MOS transistors 审中-公开
标题翻译：形成MOS晶体管的沟槽接触的方法
公开(公告)号：US20070218685A1
公开(公告)日：2007-09-20
申请号：US11384143
申请日：2006-03-17
申请人： Swaminathan Sivakumar , Charles Wallace , Alison Davis , Nadia Rahhal-Orabi
发明人： Swaminathan Sivakumar , Charles Wallace , Alison Davis , Nadia Rahhal-Orabi
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/76816 , H01L21/76895 , H01L23/485
摘要： A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings for the first and second diffusion regions. A sacrificial layer is then deposited into the first and second diffusion trench openings. Next, a second photolithography process forms a gate stack trench opening for the gate stack and a local interconnect trench opening coupling the gate stack trench opening to the first diffusion trench opening. The second photolithography process is carried out independent of the first photolithography process. The sacrificial layer is then removed and a metallization process is carried out to fill the first and second diffusion trench openings, the gate stack trench opening, and the local interconnect trench opening with a metal layer.
摘要翻译：形成晶体管触点的方法开始于提供一种晶体管，该晶体管包括栅极堆叠以及形成在衬底上的第一和第二扩散区域，以及形成在栅极堆叠和扩散区域顶部的电介质层。第一光刻工艺形成用于第一和第二扩散区域的第一和第二扩散沟槽开口。然后将牺牲层沉积到第一和第二扩散沟槽开口中。接下来，第二光刻工艺形成用于栅极堆叠的栅极堆叠沟槽开口和将栅极堆叠沟槽开口耦合到第一扩散沟槽开口的局部互连沟槽开口。第二光刻工艺是独立于第一光刻工艺进行的。然后去除牺牲层，并且进行金属化处理以填充第一和第二扩散沟槽开口，栅极堆叠沟槽开口和具有金属层的局部互连沟槽开口。

9. 发明申请

US20100171156A1 Method for Forming Semiconductor Contacts 审中-公开
标题翻译：形成半导体触点的方法
公开(公告)号：US20100171156A1
公开(公告)日：2010-07-08
申请号：US12723768
申请日：2010-03-15
申请人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
发明人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
IPC分类号： H01L23/48 , H01L21/768 , H01L21/336 , H01L29/78
CPC分类号： H01L21/76804 , H01L21/76816 , H01L29/78
摘要： In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
摘要翻译：在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

10. 发明授权

US07981756B2 Common plate capacitor array connections, and processes of making same 有权
标题翻译：普通板电容阵列连接及其制作工艺
公开(公告)号：US07981756B2
公开(公告)日：2011-07-19
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译：形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。该过程包括将电容器单元边界的第一高度降低到第二高度。普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

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