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1. 发明授权

US06274433B1 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 有权
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06274433B1
公开(公告)日：2001-08-14
申请号：US09476121
申请日：2000-01-03
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

2. 发明授权

US06034394A Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 失效
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06034394A
公开(公告)日：2000-03-07
申请号：US992950
申请日：1997-12-18
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

3. 发明申请

US20070093042A1 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US20070093042A1
公开(公告)日：2007-04-26
申请号：US11254769
申请日：2005-10-21
申请人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
发明人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

4. 发明授权

US06680509B1 Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory 有权
标题翻译：用于保护ONO结构的氮化物阻挡层免受SONOS闪存的制造中的顶部氧化物损失
公开(公告)号：US06680509B1
公开(公告)日：2004-01-20
申请号：US10158044
申请日：2002-05-30
申请人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
发明人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.
摘要翻译：一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。本发明还涉及包括氮化物阻挡层的SONOS型器件。

5. 发明授权

US06252276B1 Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide 有权
标题翻译：非易失性半导体存储器件包括非均匀氮掺杂的栅极氧化物
公开(公告)号：US06252276B1
公开(公告)日：2001-06-26
申请号：US09377183
申请日：1999-08-19
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L2978
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

6. 发明授权

US5972751A Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中将氮引入隧道氧化物的方法和装置
公开(公告)号：US5972751A
公开(公告)日：1999-10-26
申请号：US143090
申请日：1998-08-28
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

7. 发明授权

US06403420B1 Nitrogen implant after bit-line formation for ONO flash memory devices 有权
标题翻译： ONO闪存器件位线形成后的氮注入
公开(公告)号：US06403420B1
公开(公告)日：2002-06-11
申请号：US09627664
申请日：2000-07-28
申请人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
发明人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/26506 , H01L21/28282 , H01L21/76202 , H01L27/115 , H01L29/66833
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。在ONO层和接合区域已经形成之后注入氮。整个半导体结构被加热以退出氮注入损伤，并将注入的氮扩散或驱动到衬底和氧化硅界面中，以在该界面处形成强的SiN键。通过将氮气注入到ONO堆叠中，代替如常规制造的单个氧化硅层，降低了底层硅衬底的损坏。这导致相邻位线之间更好的隔离并且抑制相邻位线之间的泄漏。

8. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

9. 发明授权

US06440797B1 Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory 有权
标题翻译：用于在SONOS闪存的制造中保护ONO结构免受顶部氧化物损失的氮化物阻挡层
公开(公告)号：US06440797B1
公开(公告)日：2002-08-27
申请号：US09966702
申请日：2001-09-28
申请人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
发明人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.
摘要翻译：一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在所述氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。本发明还涉及包括氮化物阻挡层的SONOS型器件。

10. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

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