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1. 发明授权

US06274433B1 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 有权
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06274433B1
公开(公告)日：2001-08-14
申请号：US09476121
申请日：2000-01-03
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

2. 发明授权

US06034394A Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 失效
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06034394A
公开(公告)日：2000-03-07
申请号：US992950
申请日：1997-12-18
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

3. 发明授权

US06248628B1 Method of fabricating an ONO dielectric by nitridation for MNOS memory cells 有权
标题翻译：通过氮化制备ONO电介质用于MNOS记忆单元的方法
公开(公告)号：US06248628B1
公开(公告)日：2001-06-19
申请号：US09426430
申请日：1999-10-25
申请人： Arvind Halliyal , David K. Foote , Hideki Komori , Kenneth W. Au
发明人： Arvind Halliyal , David K. Foote , Hideki Komori , Kenneth W. Au
IPC分类号： H01L21336
CPC分类号： H01L29/7923 , H01L21/28282
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.
摘要翻译：在2位EEPROM器件中制造ONO浮栅电极的工艺包括提供半导体衬底和热生长覆盖半导体衬底的第一氧化硅层。在氧化氮，一氧化二氮和氨中的至少一种的环境气氛中生长第一氧化硅层之后进行热退火。在这方面，氮被并入到第一氧化硅层中，导致ONO结构的更好的性能和更高的质量。形成氮化硅层以覆盖第一氧化硅层; 并且形成第二层氧化硅以覆盖氮化硅层以完成ONO结构。

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