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1. 发明申请

US20070043933A1 INSTRUCTION SET ARCHITECTURE EMPLOYING CONDITIONAL MULTISTORE SYNCHRONIZATION 有权
标题翻译：使用条件多重同步的指令集架构
公开(公告)号：US20070043933A1
公开(公告)日：2007-02-22
申请号：US11465383
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F9/44
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30094 , G06F9/3861 , G06F12/0815
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们将所提出的机制称为条件多存储同步机制，并且定义与其一致的指令集架构的方面。

2. 发明申请

US20070043915A1 CONDITIONAL MULTISTORE SYNCHRONIZATION MECHANISMS 有权
标题翻译：条件多重同步机制
公开(公告)号：US20070043915A1
公开(公告)日：2007-02-22
申请号：US11465376
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F13/28
CPC分类号： G06F12/0864 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0804 , G06F12/0815 , G06F12/0846
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们称提出的机制是条件多存储同步机制。

3. 发明申请

US20070255907A1 Value-based memory coherence support 有权
标题翻译：基于价值的记忆一致性支持
公开(公告)号：US20070255907A1
公开(公告)日：2007-11-01
申请号：US11413243
申请日：2006-04-28
申请人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
发明人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
IPC分类号： G06F13/28
CPC分类号： G06F12/0815 , G06F12/0808 , G06F12/0822 , G06F12/0897
摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.
摘要翻译：在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

4. 发明授权

US08621317B1 Modified orthogonal coding techniques for storing data 有权
标题翻译：用于存储数据的修正正交编码技术
公开(公告)号：US08621317B1
公开(公告)日：2013-12-31
申请号：US13190151
申请日：2011-07-25
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , H03M13/2909
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for modified orthogonal coding techniques. In one aspect, a method includes receiving a block of data. A column of error-correcting row code chunks is generated using a matrix of row weights that includes weights [a b c d], wherein a and b are in a same first row and c and d are in a same second row, and wherein a and c are in a same first column and b and d are in a same second column. A row of error-correcting column code chunks is generated using a matrix of column weights that includes weights [e f g h] at positions corresponding to respective positions of [a b c d] in the matrix of row weights, wherein a ⁢ ⁢ d b ⁢ ⁢ c ≠ e ⁢ ⁢ h f ⁢ ⁢ g .
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于修改的正交编码技术。一方面，一种方法包括接收数据块。使用包括权重[abcd]的行权重矩阵来生成错误校正行代码块的列，其中a和b处于相同的第一行，c和d在相同的第二行中，并且其中a和c 在同一第一列，b和d在同一第二列。使用列权重矩阵来生成错误校正列代码块行，其中行权重矩阵中对应于[abcd]的各个位置的位置包括权重[efgh]，其中， e呃hf⁢g

5. 发明授权

US08606997B2 Cache hierarchy with bounds on levels accessed 有权
标题翻译：缓存层次结构，并且访问级别的边界
公开(公告)号：US08606997B2
公开(公告)日：2013-12-10
申请号：US12343065
申请日：2008-12-23
申请人： Robert Cypher , Haakan Zeffer , Anders Landin
发明人： Robert Cypher , Haakan Zeffer , Anders Landin
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0862
摘要： The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
摘要翻译：本发明涉及一种管理多级高速缓冲存储器系统中的数据的系统。某些高速缓存数据被指定并仅存储在多级缓存的特定级别中，从而绕过多级高速缓存的其他级别。在多处理器环境中，本发明包括高速缓存一致性操作或与仅存储在多级缓存的特定级别中的数据相关的消息。

6. 发明申请

US20060107025A1 Mechanism and method for determining stack distance including spatial locality of running software 有权
标题翻译：确定堆栈距离的机制和方法，包括运行软件的空间位置
公开(公告)号：US20060107025A1
公开(公告)日：2006-05-18
申请号：US11281749
申请日：2005-11-16
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F12/10
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each address corresponding to each received memory reference to generate a modified version of each corresponding address, and then performing a first hash function on the modified version of each corresponding address. In addition, the method may include performing a filter function on each address corresponding to each received memory reference. The method may further include selectively storing an indication representative of the modified version of each corresponding address in a hash table dependent upon results of the first hash function and the filter function. A stack distance may then be determined based upon contents of the hash table.
摘要翻译：一种用于确定堆栈距离的方法，包括运行软件的空间位置。该方法可以包括接收多个存储器引用，每个存储器引用包括对应的地址。该方法还可以包括对与每个接收到的存储器引用相对应的每个地址执行合并功能，以生成每个相应地址的修改版本，然后对每个相应地址的修改版本执行第一散列函数。此外，该方法可以包括对与每个接收的存储器参考相对应的每个地址执行滤波器功能。该方法还可以包括根据第一散列函数和滤波器函数的结果，有选择地将表示每个对应地址的修改版本的指示存储在散列表中。然后可以基于散列表的内容来确定堆栈距离。

7. 发明申请

US20050044174A1 Multi-node computer system where active devices selectively initiate certain transactions using remote-type address packets 审中-公开
标题翻译：多节点计算机系统，其中活动设备使用远程类型地址分组选择性地启动某些事务
公开(公告)号：US20050044174A1
公开(公告)日：2005-02-24
申请号：US10821729
申请日：2004-04-09
申请人： Anders Landin , Robert Cypher , Erik Hagersten , Ashok Singhal
发明人： Anders Landin , Robert Cypher , Erik Hagersten , Ashok Singhal
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/0831
摘要： A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.
摘要翻译：系统可以包括由节点间网络耦合的多个节点。每个节点包括若干活动设备，节点间网络的接口以及将活动设备耦合到接口的地址网络。包括在其中一个节点中的活动设备通过在地址网络上发送第一类型的地址分组或第二类型的地址分组来发起交易，这取决于活动设备是否包括在多节点系统中。如果活动设备包括在多节点系统中并且不与主动设备在同一节点中的其他活动设备进行窥探，则发送第一类地址分组。如果活动设备包含在单个节点系统中，则发送的第二种类型的地址分组被与活动设备在同一节点中的其他活动设备进行探测。

8. 发明授权

US06823476B2 Mechanism to improve fault isolation and diagnosis in computers 有权
标题翻译：改善电脑故障隔离和诊断的机制
公开(公告)号：US06823476B2
公开(公告)日：2004-11-23
申请号：US10328539
申请日：2002-12-23
申请人： Emrys Williams , Robert Cypher
发明人： Emrys Williams , Robert Cypher
IPC分类号： G06F1100
CPC分类号： G06F11/22 , G06F11/0724 , G06F11/0763 , G06F11/079 , G06F11/10 , G06F11/1024
摘要： A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis. If diagnosis has not been initiated, the interface initiates diagnosis and sets the flag to indicate that diagnosis has already been initiated. The data and corresponding flag are then passed to the second subsystem. If the data contains an uncorrectable error, data error handling procedures will be performed by the subsystem that requested the data, regardless of the value of the corresponding flag.
摘要翻译：一种用于改善计算系统中的硬件故障的隔离和诊断的系统和方法，其中提供了用于指示不可用数据是否先前触发导致数据不可用的硬件故障的诊断的装置。如果尚未执行诊断，则标志未设置。如果已经执行了诊断，则设置该标志。一个实施例包括用于将数据从一个子系统传送到另一个子系统的接口。当接口从第一个子系统接收数据时，检查数据以确定它是否包含不可校正的错误（包括丢失的数据）。如果数据包含不可校正的错误，接口将检查与数据相对应的标志，以确定硬件故障诊断已经开始了。如果已经启动诊断，则数据将传递到第二个子系统，而不会进一步诊断。如果诊断尚未启动，界面将启动诊断并设置标志以指示诊断已经启动。然后将数据和相应的标志传递给第二个子系统。如果数据包含不可校正的错误，数据错误处理过程将由请求数据的子系统执行，而不管对应标志的值如何。

9. 发明授权

US06393597B1 Mechanism for decoding linearly-shifted codes to facilitate correction of bit errors due to component failures 有权
标题翻译：用于解码线性移位代码以促进由于组件故障导致的位错误的校正的机制
公开(公告)号：US06393597B1
公开(公告)日：2002-05-21
申请号：US09323328
申请日：1999-06-01
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M1300
CPC分类号： G06F11/1028
摘要： A mechanism for decoding linear shifted codes employs two shift registers. The shift registers are independently controlled by an associated control unit. Initially, the received parity bits are stored in a first shift register and the global syndrome bits are stored in a second shift register. While the right-most cell in the first shift register contains a logical “0”, both shift registers are shifted right one position. When the right-most cell of the first shift register contains a “1”, the content of the right-most cell of the second shift register is recorded as a first bit of a syndrome code which identifies the position of an error with any groups with an error. If the value recorded is a “1”, a bit-wise exclusive OR operation is then performed on the values in the first and second shift registers, and the result is stored in the second shift register. Subsequently, the contents of the second shift register are shifted by one position. Similar to the previous operation, the content of the right-most cell of the second shift register is again recorded, this time as the next bit of the syndrome code. A bit-wise exclusive OR is again conditionally performed upon the values in the first and second shift registers depending upon whether the last recorded bit was a “1” (and the result is stored in the second shift register), and the contents of the second shift register are shifted. These steps are repeated until all L bits of the syndrome code identifying a failed component have been recorded (where L is the smallest integer such that 2L>=M, where M is the number of components used).
摘要翻译：用于解码线性移位码的机制采用两个移位寄存器。移位寄存器由相关的控制单元独立控制。最初，接收到的奇偶校验位存储在第一移位寄存器中，并且全局校正位存储在第二移位寄存器中。虽然第一移位寄存器中最右边的单元包含逻辑“0”，但两个移位寄存器都向右移位一个位置。当第一移位寄存器的最右边的单元包含“1”时，将第二移位寄存器的最右边单元的内容记录为校正码的第一位，其中标识与任何组的错误的位置有错误。如果记录的值为“1”，则对第一和第二移位寄存器中的值执行逐位异或运算，并将结果存储在第二移位寄存器中。随后，第二移位寄存器的内容被移位一个位置。类似于先前的操作，再次记录第二移位寄存器的最右边单元的内容，这次作为校正子代码的下一位。根据最后一个记录位是否为“1”（并将结果存储在第二移位寄存器中），根据第一和第二移位寄存器中的值再次有条件地执行逐位异或，第二移位寄存器被移位。重复这些步骤，直到记录了识别故障组件的校验码代码的所有L位（其中L是最小整数，使得2 L> = M，其中M是使用的组件数。

10. 发明授权

US08615698B1 Skewed orthogonal coding techniques 有权
标题翻译：偏斜正交编码技术
公开(公告)号：US08615698B1
公开(公告)日：2013-12-24
申请号：US13246966
申请日：2011-09-28
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H03M13/2918 , H03M13/09 , H03M13/1515
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving data chunks to be stored and generating intra-level code chunks and inter-level code chunks using the data chunks and partitions of numbers. Levels of codewords are stored. The partitions are selected so that, for at least a first set of chunks A, B, and A′ wherein A and B are in a same intra-level codeword and A and A′ are in a same inter-level codeword, there is no chunk B′ that is in both an intra-level codeword containing A′ and an inter-level codeword containing B.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于偏斜正交编码技术。在一个方面，一种方法包括接收要存储的数据块，并使用数据块和数字分区来生成级内代码块和级间代码块。存储码字级别。选择分区，使得对于至少第一组块A，B和A'，其中A和B处于相同的帧内码字，A和A'处于相同的层间码字之中，存在在包含A'的层内码字和包含B的层间码字之间的任何块B'

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