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1. 发明申请

US20070255907A1 Value-based memory coherence support 有权
标题翻译：基于价值的记忆一致性支持
公开(公告)号：US20070255907A1
公开(公告)日：2007-11-01
申请号：US11413243
申请日：2006-04-28
申请人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
发明人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
IPC分类号： G06F13/28
CPC分类号： G06F12/0815 , G06F12/0808 , G06F12/0822 , G06F12/0897
摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.
摘要翻译：在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

2. 发明申请

US20050044174A1 Multi-node computer system where active devices selectively initiate certain transactions using remote-type address packets 审中-公开
标题翻译：多节点计算机系统，其中活动设备使用远程类型地址分组选择性地启动某些事务
公开(公告)号：US20050044174A1
公开(公告)日：2005-02-24
申请号：US10821729
申请日：2004-04-09
申请人： Anders Landin , Robert Cypher , Erik Hagersten , Ashok Singhal
发明人： Anders Landin , Robert Cypher , Erik Hagersten , Ashok Singhal
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/0831
摘要： A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.
摘要翻译：系统可以包括由节点间网络耦合的多个节点。每个节点包括若干活动设备，节点间网络的接口以及将活动设备耦合到接口的地址网络。包括在其中一个节点中的活动设备通过在地址网络上发送第一类型的地址分组或第二类型的地址分组来发起交易，这取决于活动设备是否包括在多节点系统中。如果活动设备包括在多节点系统中并且不与主动设备在同一节点中的其他活动设备进行窥探，则发送第一类地址分组。如果活动设备包含在单个节点系统中，则发送的第二种类型的地址分组被与活动设备在同一节点中的其他活动设备进行探测。

3. 发明申请

US20050005075A1 Multi-node computer system employing multiple memory response states 审中-公开
标题翻译：采用多个存储器响应状态的多节点计算机系统
公开(公告)号：US20050005075A1
公开(公告)日：2005-01-06
申请号：US10821370
申请日：2004-04-09
申请人： Anders Landin , Robert Cypher , David Wood , Erik Hagersten , Mark Hill
发明人： Anders Landin , Robert Cypher , David Wood , Erik Hagersten , Mark Hill
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0817
摘要： A system may include a node and an additional node coupled by an inter-node network. The node may include an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device may send an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send data corresponding to the coherency unit to the active device dependent on memory response information associated with the coherency unit. If the transaction cannot be satisfied within the node, the memory is configured to forward a report corresponding to the address packet to the interface. In response to the report, the interface is configured to send the additional node a coherency message requesting the access right via the inter-node network.
摘要翻译：系统可以包括由节点间网络耦合的节点和附加节点。节点可以包括活动设备，到节点间网络的接口，存储器和耦合有源设备，接口和存储器的地址网络。活动设备可以发送地址分组以发起事务以获得对一致性单元的访问权限。响应于接收到地址分组，存储器被配置为根据与一致性单元相关联的存储器响应信息将对应于一致性单元的数据发送到活动设备。如果在节点内不能满足事务，则内存被配置为将与地址分组相对应的报告转发到接口。响应于该报告，该接口被配置为经由节点间网络向附加节点发送请求访问权限的一致性消息。

4. 发明授权

US08606997B2 Cache hierarchy with bounds on levels accessed 有权
标题翻译：缓存层次结构，并且访问级别的边界
公开(公告)号：US08606997B2
公开(公告)日：2013-12-10
申请号：US12343065
申请日：2008-12-23
申请人： Robert Cypher , Haakan Zeffer , Anders Landin
发明人： Robert Cypher , Haakan Zeffer , Anders Landin
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0862
摘要： The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
摘要翻译：本发明涉及一种管理多级高速缓冲存储器系统中的数据的系统。某些高速缓存数据被指定并仅存储在多级缓存的特定级别中，从而绕过多级高速缓存的其他级别。在多处理器环境中，本发明包括高速缓存一致性操作或与仅存储在多级缓存的特定级别中的数据相关的消息。

5. 发明申请

US20070022253A1 Cache coherence protocol with speculative writestream 有权
标题翻译：缓存一致性协议与推测写入
公开(公告)号：US20070022253A1
公开(公告)日：2007-01-25
申请号：US11186034
申请日：2005-07-21
申请人： Robert Cypher , Anders Landin
发明人： Robert Cypher , Anders Landin
IPC分类号： G06F13/28
CPC分类号： G06F12/0828 , G06F12/0855
摘要： A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester. If the requester detects a timeout condition, the requester may cancel the WSO transaction and unlock the coherency unit in the requesting node. The requester may further convey an acknowledgment to the home subsystem indicating no data will be returned. The home subsystem may then treat the WSO transaction as being complete.
摘要翻译：一种用于在计算系统中执行推测性写入事务的系统和方法。包括多个子系统的计算系统具有被配置为通过向相干单元的归属子系统传送WSO请求来发起写入流顺序（WSO）事务以对整个一致性单元执行写入操作的请求子系统。请求者被配置为执行写入操作，而不首先接收一致性单元的副本，并以其发起的顺序完成发起的WSO事务。家庭子系统被配置为按照它们被接收的顺序处理指向给定一致性单元的多个WSO事务。当请求者向给定的一致性单元发起WSO事务时，一致性单元被锁定。响应于接收到WSO请求，家庭子系统向请求者传送写入数据的拉取请求。如果请求者检测到超时条件，则请求者可以取消WSO事务并解除请求节点中的一致性单元。请求者还可以向家庭子系统发送确认，指示不返回任何数据。然后，家庭子系统可以将WSO交易视为完成。

6. 发明申请

US20100161904A1 CACHE HIERARCHY WITH BOUNDS ON LEVELS ACCESSED 有权
标题翻译： CACHE层次结合层次上的界限
公开(公告)号：US20100161904A1
公开(公告)日：2010-06-24
申请号：US12343065
申请日：2008-12-23
申请人： Robert Cypher , Haakan Zeffer , Anders Landin
发明人： Robert Cypher , Haakan Zeffer , Anders Landin
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0862
摘要： The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
摘要翻译：本发明涉及一种管理多级高速缓冲存储器系统中的数据的系统。某些高速缓存数据被指定并仅存储在多级缓存的特定级别中，从而绕过多级高速缓存的其他级别。在多处理器环境中，本发明包括高速缓存一致性操作或与仅存储在多级缓存的特定级别中的数据相关的消息。

7. 发明申请

US20050010615A1 Multi-node computer system implementing memory-correctable speculative proxy transactions 审中-公开
标题翻译：多节点计算机系统实现内存可纠正的投机代理事务
公开(公告)号：US20050010615A1
公开(公告)日：2005-01-13
申请号：US10821350
申请日：2004-04-09
申请人： Robert Cypher , Anders Landin
发明人： Robert Cypher , Anders Landin
IPC分类号： G06F17/30
CPC分类号： G06F12/0817 , G06F16/2308
摘要： A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network that communicates address packets between the devices. In response to receiving a coherency message that requests an access right to a coherency unit, the interface sends a proxy packet on the address network. In response to the proxy packet, the memory sends the interface data corresponding to the coherency unit and an indication of the global access state of the coherency unit within the node if the global access state is not the modified state. Otherwise, the memory sends an additional proxy packet on the address network. If the active device is the owner of the coherency unit, the active device ignores the proxy packet and responds to the additional proxy packet.
摘要翻译：节点包括若干设备，包括存储器，活动设备和被配置为在将节点耦合到另一节点的节点间网络上发送和接收一致性消息的接口以及在设备之间传送地址分组的地址网络。响应于接收到请求对一致性单元的访问权限的一致性消息，该接口在地址网络上发送代理分组。响应于代理分组，如果全局访问状态不是修改状态，则存储器发送对应于一致性单元的接口数据以及节点内的一致性单元的全局访问状态的指示。否则，内存会在地址网络上发送一个附加的代理数据包。如果活动设备是一致性单元的所有者，则活动设备忽略代理分组并响应附加代理分组。

8. 发明申请

US20070043933A1 INSTRUCTION SET ARCHITECTURE EMPLOYING CONDITIONAL MULTISTORE SYNCHRONIZATION 有权
标题翻译：使用条件多重同步的指令集架构
公开(公告)号：US20070043933A1
公开(公告)日：2007-02-22
申请号：US11465383
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F9/44
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30094 , G06F9/3861 , G06F12/0815
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们将所提出的机制称为条件多存储同步机制，并且定义与其一致的指令集架构的方面。

9. 发明申请

US20070043915A1 CONDITIONAL MULTISTORE SYNCHRONIZATION MECHANISMS 有权
标题翻译：条件多重同步机制
公开(公告)号：US20070043915A1
公开(公告)日：2007-02-22
申请号：US11465376
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F13/28
CPC分类号： G06F12/0864 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0804 , G06F12/0815 , G06F12/0846
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们称提出的机制是条件多存储同步机制。

10. 发明授权

US08621317B1 Modified orthogonal coding techniques for storing data 有权
标题翻译：用于存储数据的修正正交编码技术
公开(公告)号：US08621317B1
公开(公告)日：2013-12-31
申请号：US13190151
申请日：2011-07-25
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , H03M13/2909
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for modified orthogonal coding techniques. In one aspect, a method includes receiving a block of data. A column of error-correcting row code chunks is generated using a matrix of row weights that includes weights [a b c d], wherein a and b are in a same first row and c and d are in a same second row, and wherein a and c are in a same first column and b and d are in a same second column. A row of error-correcting column code chunks is generated using a matrix of column weights that includes weights [e f g h] at positions corresponding to respective positions of [a b c d] in the matrix of row weights, wherein a ⁢ ⁢ d b ⁢ ⁢ c ≠ e ⁢ ⁢ h f ⁢ ⁢ g .
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于修改的正交编码技术。一方面，一种方法包括接收数据块。使用包括权重[abcd]的行权重矩阵来生成错误校正行代码块的列，其中a和b处于相同的第一行，c和d在相同的第二行中，并且其中a和c 在同一第一列，b和d在同一第二列。使用列权重矩阵来生成错误校正列代码块行，其中行权重矩阵中对应于[abcd]的各个位置的位置包括权重[efgh]，其中， e呃hf⁢g

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