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1. 发明授权

US06225168B1 Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof 失效
标题翻译：具有金属栅电极和钛或氮化钽栅介质阻挡层的半导体器件及其制造方法
公开(公告)号：US06225168B1
公开(公告)日：2001-05-01
申请号：US09090792
申请日：1998-06-04
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May , Fred Hause , Dim-Lee Kwong
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May , Fred Hause , Dim-Lee Kwong
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28229 , H01L29/4941 , H01L29/66545 , H01L29/6659
摘要： Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.
摘要翻译：提供具有金属栅极电极和钛或氮化钽栅极电介质阻挡层的半导体器件以及用于制造这种器件的工艺。例如，与常规晶体管相比，使用金属栅电极与钛或氮化钽栅极电介质阻挡层可以提供具有增加的工作速度的高可靠性半导体器件。

2. 发明授权

US06911707B2 Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance 有权
标题翻译：具有良好的界面性能的超薄高K栅极电介质，可提高半导体器件的性能
公开(公告)号：US06911707B2
公开(公告)日：2005-06-28
申请号：US09207972
申请日：1998-12-09
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.
摘要翻译：提供具有渐变介电常数的超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。在半导体衬底上形成薄的含氮氧化物，优选具有小于约10埃的厚度。可以在含氮氧化物上形成厚度小于约30埃的氮化硅层。氧化物和氮化物层在氨和一氧化二氮环境中退火，并且使用流动气体蚀刻工艺来减少氮化物层的厚度。与二氧化硅电介质相比，所得到的双层栅极电介质被认为提供增加的电容，同时保持与底层衬底的有利的界面性质。在替代实施例中，用不同的高介电常数材料代替氮化硅。或者，可以使用氮化物和不同的高介电常数材料，从而形成三层电介质。

3. 发明授权

US06218720B1 Semiconductor topography employing a nitrogenated shallow trench isolation structure 有权
标题翻译：半导体地形采用氮化浅沟槽隔离结构
公开(公告)号：US06218720B1
公开(公告)日：2001-04-17
申请号：US09176131
申请日：1998-10-21
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/3145 , H01L21/3185
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。主要包括氮化物的衬垫形成在沟槽底板和侧壁上。然后将衬里氧化。沟槽电介质可以形成在沟槽内并且被平坦化以完成隔离结构。

4. 发明授权

US06207995B1 High K integration of gate dielectric with integrated spacer formation for high speed CMOS 有权
标题翻译：高K集成栅极电介质与高速CMOS的集成间隔物形成
公开(公告)号：US06207995B1
公开(公告)日：2001-03-27
申请号：US09255917
申请日：1999-02-23
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L29/42368 , H01L29/516 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66598 , H01L29/78391
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，该方法包括以下步骤：在衬底上形成具有第一向外锥形侧壁和第二向外渐缩侧壁的栅极绝缘层。在栅极绝缘层上形成栅电极。通过将离子注入衬底而在衬底中形成第一源/漏区和第二源极/漏极区，其中离子的第一部分穿过第一侧壁，并且离子的第二部分通过第二侧壁。该方法提供了将间隔物结构结合到栅介质层中。可以消除传统的间隔物制造，并用单个植入物建立分级的源极/漏极区域。

5. 发明授权

US06245652B1 Method of forming ultra thin gate dielectric for high performance semiconductor devices 有权
标题翻译：形成用于高性能半导体器件的超薄栅极电介质的方法
公开(公告)号：US06245652B1
公开(公告)日：2001-06-12
申请号：US09598531
申请日：2000-06-21
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises forming a first layer of nitrogen doped silicon dioxide above a semiconducting substrate, reducing the thickness of the first layer, forming a second layer comprised of a material having a dielectric constant greater than seven above the first layer of silicon dioxide. The method further comprises forming a third layer comprised of a gate conductor material above the second layer, and patterning the first, second and third layers to define a gate conductor and a composite gate dielectric comprised of the first and second layers, and forming at least one source/drain region. The semiconductor device has a composite gate dielectric comprised of a first process layer comprised of a nitrogen doped oxide and a second process layer comprised of a material having a dielectric constant greater than seven. The device further comprises a gate conductor positioned above the composite gate dielectric, and at least one source/drain region formed in the substrate.
摘要翻译：本发明涉及具有超薄，可靠的栅极电介质的半导体器件及其制造方法。在一个说明性实施例中，本方法包括在半导体衬底上形成氮掺杂二氧化硅的第一层，减小第一层的厚度，形成第二层，第二层由介电常数大于第一层以上的材料构成的二氧化硅。该方法还包括在第二层上形成由栅极导体材料构成的第三层，以及对第一层，第二层和第三层进行构图以限定由第一层和第二层构成的栅极导体和复合栅极电介质，并形成至少一个源/漏区。该半导体器件具有复合栅极电介质，该复合栅极电介质由包含氮掺杂氧化物的第一工艺层和由介电常数大于7的材料构成的第二工艺层组成。该器件还包括位于复合栅极电介质上方的栅极导体，以及形成在衬底中的至少一个源极/漏极区。

6. 发明授权

US6015739A Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant 失效
标题翻译：制造半导体MOS晶体管的栅极电介质的方法，包括梯度介电常数
公开(公告)号：US6015739A
公开(公告)日：2000-01-18
申请号：US959796
申请日：1997-10-29
申请人： Mark I. Gardner , H. Jim Fulford , Dim-Lee Kwong
发明人： Mark I. Gardner , H. Jim Fulford , Dim-Lee Kwong
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.
摘要翻译：一种用于制造MOS晶体管的栅极电介质叠层的工艺。在半导体衬底的上表面上形成自然氧化膜。然后将氮化硅层沉积在自然氧化膜上。然后在氮化硅膜上形成最终的电介质膜。最终电介质膜的介电常数在大约20-200的范围内。然后将衬底在惰性环境中退火以产生栅极电介质叠层。电介质堆叠的等效二氧化硅厚度通常在约5-20埃的范围内，由此制造适合用于深亚微米晶体管的栅极电介质叠层，其膜厚度基本上超过电当量的二氧化硅膜。用于最终电介质膜的合适材料包括氧化物，其包含氧和诸如铍，镁，钙，锆，钛或钽的元素。

7. 发明授权

US5591681A Method for achieving a highly reliable oxide film 失效
标题翻译：实现高可靠性氧化膜的方法
公开(公告)号：US5591681A
公开(公告)日：1997-01-07
申请号：US253771
申请日：1994-06-03
申请人： Dirk J. Wristers , Dim-Lee Kwong , H. Jim Fulford, Jr.
发明人： Dirk J. Wristers , Dim-Lee Kwong , H. Jim Fulford, Jr.
IPC分类号： C23C16/56 , H01L21/28 , H01L21/318 , H01L21/324 , H01L21/336 , H01L21/8247 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/3115
CPC分类号： H01L21/28185 , C23C16/56 , H01L27/11521 , H01L27/11524 , H01L29/518 , H01L21/28194 , H01L21/28202 , H01L21/28211 , Y10S438/909 , Y10S438/954
摘要： High quality oxides utilized in tunnel oxides and CMOS gate oxides are formed using a process that includes annealing a semiconductor substrate, after the oxide has been formed, in an ambient comprised of NO to form a surface layer in the oxide containing a concentration of nitrogen. A high-quality tunnel oxide, suitable for EEPROM devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer by first oxidizing the semiconductor body to form an oxide upon the surface region of the semiconductor body over the heavily-doped N+ layer. Next, the semiconductor body is annealed, under a gettering ambient, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent. The semiconductor body is then oxidized, under an oxidizing ambient, to thicken the oxide. The annealing step in NO improves characteristics for both the gate and tunnel oxides of the device at a temperature substantially reduced from prior art methods and in an ambient atmosphere containing significantly more NO. The NO anneal can be performed in a variety of ways including an RTP anneal, a furnace anneal and can be performed on processes where the oxides are formed using CVD and PECVD.
摘要翻译：在隧道氧化物和CMOS栅极氧化物中使用的高质量氧化物使用包括在形成氧化物的氧化物在由NO组成的环境中退火半导体衬底以在含有一定浓度的氮的氧化物中形成表面层的工艺来形成。通过首先氧化半导体体以在半导体主体的表面区域上形成氧化物，在重掺杂的N +层上的半导体本体的表面区域上形成适用于EEPROM器件的高品质隧道氧化物，掺杂的N +层。接下来，在吸气环境下，将半导体本体退火以使氧化物致密化并在其表面上掺杂氧化物，并在其表面附近用吸杂剂掺杂一部分。然后在氧化环境下氧化半导体体，使氧化物变稠。 NO中的退火步骤在从现有技术方法显着降低的温度下和在含有显着更多的NO的环境气氛中改善器件的栅极和隧道氧化物的特性。 NO退火可以以各种方式进行，包括RTP退火，炉退火，并且可以在使用CVD和PECVD形成氧化物的工艺上进行。

8. 发明授权

US06252283B1 CMOS transistor design for shared N+/P+ electrode with enhanced device performance 有权
标题翻译： CMOS晶体管设计用于共享的N + / P +电极，具有增强的器件性能
公开(公告)号：US06252283B1
公开(公告)日：2001-06-26
申请号：US09234855
申请日：1999-01-22
申请人： Mark I. Gardner , Dim-Lee Kwong , Frederick N. Hause
发明人： Mark I. Gardner , Dim-Lee Kwong , Frederick N. Hause
IPC分类号： H01L2701
CPC分类号： H01L21/28035 , H01L21/823842 , H01L21/84
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate dielectric layer on the substrate and forming a gate electrode on the gate dielectric layer with a lower surface, a midpoint, and a quantity of p-type impurity. A quantity of nitrogen is introduced into the gate electrode whereby the quantity nitrogen has a peak concentration proximate the lower surface. A quantity of germanium is introduced into the gate electrode and first and second source/drain regions are formed in the substrate. The method enables simultaneous formation of n-channel and p-channel gate electrodes with work functions tailored for both types of devices.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，该方法包括以下步骤：在衬底上形成栅极电介质层，并在具有下表面，中点和一定量的p型杂质的栅极电介质层上形成栅电极。一定量的氮气被引入到栅极中，由此氮气的量值接近下表面。将一定数量的锗引入栅电极中，并且在衬底中形成第一和第二源/漏区。该方法能够同时形成具有为两种类型的器件定制的工作功能的n沟道和p沟道栅电极。

9. 发明授权

US5679585A Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants 失效
标题翻译：在半导体表面上形成金属硅化物的方法，对预先存在的植入物具有最小的影响
公开(公告)号：US5679585A
公开(公告)日：1997-10-21
申请号：US746774
申请日：1996-11-15
申请人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers , Dim-Lee Kwong
发明人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers , Dim-Lee Kwong
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28518 , Y10S438/909
摘要： An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.
摘要翻译：提供了一种在半导体形貌上制造金属硅化物的方法。该方法有利地在基本上较低的温度下进行退火循环。通过采用高压退火室，在半导体形貌特别是在小的硅化物形成区域中实现了温度平衡。较高的压力有助于确保加热的流动气体在要形成硅化物的较小几何形状上的热接触。即使在相对较低的温度条件下，也可能在更高的压力下发生大量金属硅化物的形成。较低的温度过程有助于确保预先存在的植入区域保持在其初始位置。因此，目前的金属硅化物工艺和较低温度退火非常适合于避免杂质迁移问题，例如阈值偏移，寄生结电容增强和栅极氧化物降解。

10. 发明申请

US20090163005A1 Schottky barrier source/drain N-MOSFET using ytterbium silicide 审中-公开
标题翻译：肖特基势垒源/漏极使用镱硅化物N-MOSFET
公开(公告)号：US20090163005A1
公开(公告)日：2009-06-25
申请号：US12322932
申请日：2009-02-09
申请人： Shiyang Zhu , Jingde Chen , Sungjoo Lee , Ming Fu Li , Jagar Singh , Chunxiang Zhu , Dim-Lee Kwong
发明人： Shiyang Zhu , Jingde Chen , Sungjoo Lee , Ming Fu Li , Jagar Singh , Chunxiang Zhu , Dim-Lee Kwong
IPC分类号： H01L21/28
CPC分类号： H01L21/28518 , H01L21/28088 , H01L21/28185 , H01L29/47 , H01L29/4966 , H01L29/517 , H01L29/66643 , H01L29/7839
摘要： A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
摘要翻译：提出了一种制造用于源极和漏极的镱硅化物（YbSi2-x）的N型肖特基势垒源极/漏极晶体管（N-SSDT）的方法。 YbSi2-x的制造与正常的CMOS工艺兼容，但是不需要ErSi2-x制造所需的超高真空。为了防止在原位退火过程中镱的氧化并提高膜质量，已经开发了合适的覆盖层叠层。

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