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1. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

2. 发明授权

US07129538B2 Dense arrays and charge storage devices 有权
公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

3. 发明授权

US08503215B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US08503215B2
公开(公告)日：2013-08-06
申请号：US13526671
申请日：2012-06-19
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括转向元件和与该转向元件串联耦合的非易失性状态变化元件。转向元件和状态改变元件设置在垂直定向的支柱中。还提供其他方面。

4. 发明申请

US20120250396A1 VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US20120250396A1
公开(公告)日：2012-10-04
申请号：US13526671
申请日：2012-06-19
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括转向元件和与该转向元件串联耦合的非易失性状态变化元件。转向元件和状态改变元件设置在垂直定向的支柱中。还提供其他方面。

5. 发明申请

US20120223380A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20120223380A1
公开(公告)日：2012-09-06
申请号：US13468731
申请日：2012-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

6. 发明授权

US07190602B2 Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement 有权
标题翻译：集成电路结合具有双重相对的解码器布置的三维存储器阵列
公开(公告)号：US07190602B2
公开(公告)日：2007-03-13
申请号：US10774818
申请日：2004-02-09
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： G11C5/06
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

7. 发明授权

US06591394B2 Three-dimensional memory array and method for storing data bits and ECC bits therein 有权
标题翻译：用于在其中存储数据位和ECC位的三维存储器阵列和方法
公开(公告)号：US06591394B2
公开(公告)日：2003-07-08
申请号：US09747574
申请日：2000-12-22
申请人： Thomas H. Lee , James M. Cleeves , Mark G. Johnson
发明人： Thomas H. Lee , James M. Cleeves , Mark G. Johnson
IPC分类号： G11C2900
CPC分类号： H01L27/10 , G06F11/1072
摘要： A three-dimensional memory array and method for storing data bits and ECC bits therein is provided. A three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is described. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word.
摘要翻译：提供了一种用于存储数据位和ECC位的三维存储器阵列和方法。描述了包括多个垂直堆叠的存储单元层的类型的三维存储器阵列。三维存储器阵列包括布置在多个物理上独立的子阵列中的多个存储器单元，并且字的数据位和错误校验和校正（ECC）位被存储在物理上独立的子 - 阵营通过从字中空间扩散数据位和ECC位，减少字内多位错误的可能性。这是有利的，因为大多数ECC电路仅能够校正给定字中的单位错误。

8. 发明授权

US07978492B2 Integrated circuit incorporating decoders disposed beneath memory arrays 有权
标题翻译：集成电路，包含设置在存储器阵列下方的解码器
公开(公告)号：US07978492B2
公开(公告)日：2011-07-12
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： G11C5/06
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

9. 发明申请

US20100171152A1 INTEGRATED CIRCUIT INCORPORATING DECODERS DISPOSED BENEATH MEMORY ARRAYS 有权
标题翻译：集成电路整合解码器处理BENEATH存储器阵列
公开(公告)号：US20100171152A1
公开(公告)日：2010-07-08
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： H01L27/10
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

10. 发明授权

US06483736B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
公开(公告)号：US06483736B2
公开(公告)日：2002-11-19
申请号：US09939431
申请日：2001-08-24
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C1100
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

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