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1. 发明申请

US20080168262A1 Methods and Apparatus for Software Control of a Non-Functional Operation on Memory 审中-公开
标题翻译：用于存储器中非功能操作的软件控制的方法和装置
公开(公告)号：US20080168262A1
公开(公告)日：2008-07-10
申请号：US11620117
申请日：2007-01-05
申请人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
发明人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004
摘要： In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the bits of data serve as control bits for the memory; and (2) applying the bits of data to respective pins of the memory so as to cause the non-functional operation to be performed on the memory. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使用软件来控制计算机系统的存储器上的非功能操作的第一方法。第一种方法包括以下步骤：（1）使用处理器将数据位写入到处理器外部的至少一个寄存器，其中数据位用作存储器的控制位; 以及（2）将数据位施加到存储器的相应引脚，以使得对存储器执行非功能性操作。提供了许多其他方面。

2. 发明申请

US20080183916A1 Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开
标题翻译：使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器
公开(公告)号：US20080183916A1
公开(公告)日：2008-07-31
申请号：US11668531
申请日：2007-01-30
申请人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/00
CPC分类号： G06F11/106
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种接口处理器和存储器的第一种方法。第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。提供了许多其他方面。

3. 发明授权

US07840744B2 Rank select operation between an XIO interface and a double data rate interface 失效
标题翻译： XIO接口和双数据速率接口之间的等级选择操作
公开(公告)号：US07840744B2
公开(公告)日：2010-11-23
申请号：US11668725
申请日：2007-01-30
申请人： Mark David Bellows , Kent Harold Haselhorst , John David Irish , David Alan Norgaard
发明人： Mark David Bellows , Kent Harold Haselhorst , John David Irish , David Alan Norgaard
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种接口处理器和存储器的第一种方法。第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。提供了许多其他方面。

4. 发明申请

US20080183985A1 Rank Select Operation Between an XIO Interface and a Double Data Rate Interface 失效
标题翻译：等级选择XIO接口和双数据速率接口之间的操作
公开(公告)号：US20080183985A1
公开(公告)日：2008-07-31
申请号：US11668725
申请日：2007-01-30
申请人： Mark David Bellows , Kent Harold Haselhorst , John David Irish , David Alan Norgaard
发明人： Mark David Bellows , Kent Harold Haselhorst , John David Irish , David Alan Norgaard
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种接口处理器和存储器的第一种方法。第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。提供了许多其他方面。

5. 发明授权

US07330478B2 Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor 失效
标题翻译：方法，装置和计算机程序产品，用于实现网络处理器中帧改变代码的指针和投注模型
公开(公告)号：US07330478B2
公开(公告)日：2008-02-12
申请号：US10667024
申请日：2003-09-18
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56 , G06F15/16
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。为选择用于发送的分组提供当前指针和分支。保持当前指针用于跟踪分组中帧更改操作的当前位置。保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

6. 发明授权

US08170024B2 Implementing pointer and stake model for frame alteration code in a network processor 失效
标题翻译：在网络处理器中实现帧更改代码的指针和投注模型
公开(公告)号：US08170024B2
公开(公告)日：2012-05-01
申请号：US11934810
申请日：2007-11-05
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。为选择用于发送的分组提供当前指针和分支。保持当前指针用于跟踪分组中帧更改操作的当前位置。保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

7. 发明申请

US20090144452A1 IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT 失效
标题翻译：基于发送端口实现条件分组替换
公开(公告)号：US20090144452A1
公开(公告)日：2009-06-04
申请号：US12275241
申请日：2008-11-21
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

8. 发明授权

US07475161B2 Implementing conditional packet alterations based on transmit port 失效
标题翻译：基于发送端口实现条件数据包更改
公开(公告)号：US07475161B2
公开(公告)日：2009-01-06
申请号：US10655054
申请日：2003-09-04
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

9. 发明授权

US07757006B2 Implementing conditional packet alterations based on transmit port 失效
标题翻译：基于发送端口实现条件数据包更改
公开(公告)号：US07757006B2
公开(公告)日：2010-07-13
申请号：US12275241
申请日：2008-11-21
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

10. 发明授权

US08792332B2 Implementing lane shuffle for fault-tolerant communication links 有权
标题翻译：实施容错通信链路的车道洗牌
公开(公告)号：US08792332B2
公开(公告)日：2014-07-29
申请号：US12884389
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
IPC分类号： H04L12/26 , H04W24/08 , H04W24/00 , H04W28/04
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译：一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。移位模板通过由失败掩码控制的一组移位器进行级联。

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