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1. 发明申请

US20120069729A1 IMPLEMENTING LANE SHUFFLE FOR FAULT-TOLERANT COMMUNICATION LINKS 有权
标题翻译：实施容错通信链路的LANE SHUFFLE
公开(公告)号：US20120069729A1
公开(公告)日：2012-03-22
申请号：US12884389
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
IPC分类号： H04L12/26
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译：一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。移位模板通过由失败掩码控制的一组移位器进行级联。

2. 发明授权

US08792332B2 Implementing lane shuffle for fault-tolerant communication links 有权
标题翻译：实施容错通信链路的车道洗牌
公开(公告)号：US08792332B2
公开(公告)日：2014-07-29
申请号：US12884389
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
IPC分类号： H04L12/26 , H04W24/08 , H04W24/00 , H04W28/04
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译：一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。移位模板通过由失败掩码控制的一组移位器进行级联。

3. 发明申请

US20080183916A1 Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开
标题翻译：使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器
公开(公告)号：US20080183916A1
公开(公告)日：2008-07-31
申请号：US11668531
申请日：2007-01-30
申请人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/00
CPC分类号： G06F11/106
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种接口处理器和存储器的第一种方法。第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。提供了许多其他方面。

4. 发明申请

US20080168206A1 Methods and Apparatus for Interfacing a Processor and a Memory 审中-公开
标题翻译：用于接口处理器和存储器的方法和装置
公开(公告)号：US20080168206A1
公开(公告)日：2008-07-10
申请号：US11620110
申请日：2007-01-05
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/14
CPC分类号： G06F13/4059
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种接口处理器和存储器的第一种方法。第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。提供了许多其他方面。

5. 发明授权

US08493842B2 Implementing exchange of failing lane information for fault-tolerant communication links 失效
标题翻译：实施容错通信链路故障通道信息交换
公开(公告)号：US08493842B2
公开(公告)日：2013-07-23
申请号：US12884547
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming
IPC分类号： G06F11/00
CPC分类号： H04L25/14 , G06F11/2007
摘要： A method and circuit for implementing exchange of failing lane information for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. An ordered set for lane and link training includes a novel lane mask field for lane and link training. Ordered sets are exchanged during lane and link training for a fault-tolerant communication link to establish synchronization between a transmitter and a receiver. In a link training step, the bus link layer exchanges an ordered set with a plurality of bits of lane mask information included in predefined bytes, such as bytes 8 and 9 of the lane mask field. Upon receiving the ordered set with the plurality of bits of lane mask information, the transmitter lanes are reconfigured to align with the received mask information.
摘要翻译：一种用于实现用于容错通信链路的故障通道信息交换的方法和电路，以及提供了所述主题电路所在的设计结构。车道和链接训练的订购套件包括一个用于车道和链接训练的新型车道遮罩场。在容错通信链路的通道和链路训练期间交换有序集，以建立发射机和接收机之间的同步。在链路训练步骤中，总线链路层与预定义字节（包括通道掩码字段的字节8和9）中包含的多个通道掩码信息比特交换有序集合。在接收到具有多个通道掩码信息的位的有序集合之后，重新配置发射器通道以与接收到的掩模信息对准。

6. 发明申请

US20120069734A1 IMPLEMENTING EXCHANGE OF FAILING LANE INFORMATION FOR FAULT-TOLERANT COMMUNICATION LINKS 失效
标题翻译：实施故障通信链路故障交换信息
公开(公告)号：US20120069734A1
公开(公告)日：2012-03-22
申请号：US12884547
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming
IPC分类号： G06F11/00
CPC分类号： H04L25/14 , G06F11/2007
摘要： A method and circuit for implementing exchange of failing lane information for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. An ordered set for lane and link training includes a novel lane mask field for lane and link training. Ordered sets are exchanged during lane and link training for a fault-tolerant communication link to establish synchronization between a transmitter and a receiver. In a link training step, the bus link layer exchanges an ordered set with a plurality of bits of lane mask information included in predefined bytes, such as bytes 8 and 9 of the lane mask field. Upon receiving the ordered set with the plurality of bits of lane mask information, the transmitter lanes are reconfigured to align with the received mask information.
摘要翻译：一种用于实现用于容错通信链路的故障通道信息交换的方法和电路，以及提供了所述主题电路所在的设计结构。车道和链接训练的订购套件包括一个用于车道和链接训练的新型车道遮罩场。在容错通信链路的通道和链路训练期间交换有序集，以建立发射机和接收机之间的同步。在链路训练步骤中，总线链路层与预定义字节（包括通道掩码字段的字节8和9）中包含的多个通道掩码信息比特交换有序集合。在接收到具有多个通道掩码信息的位的有序集合之后，重新配置发射器通道以与接收到的掩模信息对准。

7. 发明授权

US07752379B2 Managing write-to-read turnarounds in an early read after write memory system 有权
标题翻译：在写入内存系统之后的早期读取中管理写入阅读的周转时间
公开(公告)号：US07752379B2
公开(公告)日：2010-07-06
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

8. 发明申请

US20090119442A1 Managing Write-to-Read Turnarounds in an Early Read After Write Memory System 有权
标题翻译：在写入内存系统后的早期读取中管理写入阅读的周转
公开(公告)号：US20090119442A1
公开(公告)日：2009-05-07
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/06
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

9. 发明授权

US07490204B2 Using constraints to simplify a memory controller 失效
标题翻译：使用约束来简化内存控制器
公开(公告)号：US07490204B2
公开(公告)日：2009-02-10
申请号：US11101614
申请日：2005-04-07
申请人： Mark David Bellows , Ryan Abel Heckendorf
发明人： Mark David Bellows , Ryan Abel Heckendorf
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1694
摘要： A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.
摘要翻译：存储器控制器设计工具检索由存储器控制器支持的参数范围，并识别麻烦的参数值组合。内存控制器设计工具建议：1）向存储器控制器添加逻辑以解决冲突，2）结合一个约束，减少/消除命令冲突，数据冲突和/或需要检查特定的时序参数，或3）两者的结合。存储器控制器设计工具可以与存储器控制器设计器一起工作以定义和使用约束。

10. 发明授权

US07305517B2 Structure of sequencers that perform initial and periodic calibrations in a memory system 失效
标题翻译：在存储器系统中执行初始和定期校准的顺控程序的结构
公开(公告)号：US07305517B2
公开(公告)日：2007-12-04
申请号：US10988290
申请日：2004-11-12
申请人： Mark David Bellows , Ryan Abel Heckendorf
发明人： Mark David Bellows , Ryan Abel Heckendorf
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1689
摘要： A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.
摘要翻译：提供了定序器的结构，方法和计算机程序，用于在XDR TM存储器系统中执行初始和周期性校准。执行这些校准的存储器控制器被分成相同的独立半部，每个半部分包含电流/阻抗校准（i / z Cal）定序器和六个音序器。 i / z Cal序列器包含执行XIO电流和终止校准的三个路径，以及XDR（TM）DRAM电流和终端阻抗校准。每个Bank序列器都包含正常的读写操作路径，用于实现接收建立，接收保持，发送设置，发送保持，XIO接收和XIO发送定时校准。必须进行初始和周期性校准，以确保XIO和XDR（TM）DRAM之间数据的精确传输。

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